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ATtiny13

Instruction list in AVR assembler

Rx: result register; Ry: any register; Rh: Register R16 to R31; RdL/H: Register pair low/High (R25:R24, R27:R26, R29:R28, R31:R30); P: Port; PL: Lower port; X: R27:R26; Y: R29:R28; Z: R31:R30; SP: Stack pointer; C: Carry flag; I: Interrupt flag; K: Constant
Instruction list
Mnem.P1P2DescriptionActionFlags affectedClkLimitationsWords
Arithmetical and logical operations
ADDRxRyAdd registerRx ← Rx + RyZ,C,N,V,S,H11
ADCRxRyAdd register and carryRx ← Rx + Ry + CZ,C,N,V,S,H11
ADIWRdLKAdd constant to register pairRdH:RdL ← RdH:RdL + KZ,C,N,V,S2RdL=24/26/28/30, K: 0 to 631
SUBRxRySubtract registerRx ← Rx - RyZ,C,N,V,S,H11
SUBIRhKSubtract constantRh ← Rh - KZ,C,N,V,S,H1R: 16 to 311
SBCRxRySubtract register and carryRx ← Rx - Ry - CZ,C,N,V,S,H11
SBCIRhKSubtract constant and carryRh ← Rh - K - CZ,C,N,V,S,H1R: 16 to 311
CPRy1Ry2Compare registerRx - RyZ,C,N,V,S,H11
CPCRy1Ry2Compare register and carryRy1 - Ry2 - CZ,C,N,V,S,H11
CPIRhKCompare with constantRx - KZ,C,N,V,S,H1R: 16 to 31, K: 0 to 2551
SBIWRdLKSubtract constant from register pairRdH:RdL ← RdH:RdL - KZ,C,N,V,S2RdL=24/26/28/30, K: 0 to 631
ANDRxRyBinary AND registerRx ← Rx AND RyZ,N,V,S11
ANDIRhKBinary AND with constantRh ← Rh UND KZ,N,V,S1R: 16 to 31, K: 0 to 2551
ORRxRyBinary ORRx ← Rx OR RyZ,N,V,S11
ORIRhKBinary OR with constantRh ← Rh OR KZ,N,V,S1R: 16 to 31, K: 0 to 2551
EORRxRyExclusive-ORRx ← Rx XOR RyZ,N,V,S11
COMRxOne's complementRx ← 255 - RxZ,C,N,V,S11
NEGRxTwo's complementRx ← 256 - RxZ,C,N,V,S,H11
SBRRhKSet bits in constant KRh ← Rh OR KZ,N,V,S1R: 16 to 31, K: 0 to 2551
CBRRhKClear bits in constant KRh ← Rh AND (NEG K)Z,N,V,S1R: 16 to 31, K: 0 to 2551
INCRxIncrease by oneRx ← Rx + 1Z,N,V,S11
DECRxDecrease by oneRx ← Rx - 1Z,N,V,S11
TSTRyCompare with zeroRx OR RxZ,N,V,S11
CLRRxClear all bitsRx ← 0 Z,N,V,S11
SERRhSet all bitsRh ← 255-1R: 16 to 311
MULRy1Ry2Multiply 8 bitsR1:R0 ← Ry1 * Ry2Z,C21
MULSRy1Ry2Multiply signedR1:R0 ← Ry1 * Ry2Z,C2Ry1,Ry2: 16 to 311
MULSURxRyMultiplipy unsigned and signedR1:R0 ← Ry1 * Ry2Z,C2Ry1,Ry2: 16 to 311
FMULRy1Ry2Floating point multiplicationR1:R0 ← Ry1 * Ry2Z,C2Ry1,Ry2: 16 to 231
FMULSRy1Ry2Floating point multiplication signedR1:R0 ← Ry1 * Ry2Z,C2Ry1,Ry2: 16 to 231
FMULSURy1Ry2Floating point multiplication signed and unsignedR1:R0 ← Ry1 * Ry2Z,C2Ry1,Ry2: 16 to 231
DESKData encoding and decoding(R7:R0, R15:R8)-1/2(MEGA/XMEGA only), K<161
Jump instructions
RJMPKRelative jump(PC) ← (PC) +/- K-2K: -2048 to 20471
IJMPIndirect jump(PC) ← Z-21
EIJMPExtended indirect jump(PC) ← EIND + Z-2(XMEGA only)1
JMPKDirect (wide) jump(PC) ← K-3K: 0 to 655352
RCALLKRelative call(Stack) ← (PC), (PC) ← (PC) +/- K-2/3/41
ICALLIndirect call(Stack) ← (PC), (PC) ← Z-2/3/41
EICALLExtended indirect call(Stack) ← (PC), (PC) ← EIND+Z-3/41
CALLKWide call(Stack) ← (PC), (PC) ← K-3/4/52
RETReturn from call(PC) ← (Stack)-41
RETIReturn from interrupt service routine(PC) ← (Stack), I ← 1-41
CPSERy1Ry2Jump over next instruction if equalRy1=Ry2: (PC) ← (PC + 2)-2/31
SBRCRyBJump over next instruction if bit clear(Bit)=0: (PC) ← (PC+2)-2/31
SBRSRyBJump over next instruction if bit set(Bit)=1: (PC) ← (PC+2)-2/31
SBICPLBJump over next instruction if portbit clear(Bit)=0: (PC) ← (PC+1)-2/31
SBISPLBJump over next instruction if portbit set(Bit)=1: (PC) ← (PC+1)-2/31
BRBSKBJump relative if bit in SREG set(SREG-Bit=1): (PC) ← (PC) +/- K-1/21
BRBCKBJump relative if bit in SREG clear(SREG-Bit=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BREQKJump relative if Z in SREG set(SREG-Z=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRNEKJump relative if Z in SREG clear(SREG-Z=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRCSKJump relative if C in SREG set(SREG-C=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRCCKJump relative if C in SREG clear(SREG-C=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRSHKJump relative if C in SREG clear(SREG-C=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRLOKJump relative if C in SREG set(SREG-C=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRMIKJump relative if N in SREG set(SREG-N=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRPLKJump relative if Z in SREG clear(SREG-N=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRGEKJump relative if S in SREG clear(SREG-S=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRLTKJump relative if S in SREG set(SREG-S=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRHSKJump relative if H in SREG set(SREG-H=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRHCKJump relative if H in SREG clear(SREG-H=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRTSKJump relative if T in SREG set(SREG-T=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRTCKJump relative if T in SREG clear(SREG-T=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRVSKJump relative if V in SREG set(SREG-V=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRVCKJump relative if V in SREG clear(SREG-V=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRIEKJump relative if I in SREG set(SREG-I=1): (PC) ← (PC) +/- K-1/2K: -63 to + 641
BRIDKJump relative if I in SREG clear(SREG-I=0): (PC) ← (PC) +/- K-1/2K: -63 to + 641
Data copy and load instructions
MOVRxRyCopy registerRx ← Ry-11
MOVWRxRyCopy register pairRx+1:Rx ← Ry+1:Ry-11
LDIRhKLoad constantRh ← K-1R: 16 to 31, K: 0 to 2551
LDSRhACopy SRAM byteRx ← (SRAM-A)-2/3/4R: 16 to 312
LDRxXCopy SRAM byte on address XRx ← (X)-2/3/41
LDRxX+Copy SRAM byte on address X and increment addressRx ← (X), X = X + 1-2/31
LDRx-XDecrement X and copy SRAM byte from address XX = X - 1, Rx ← (X)-2/3/41
LDRxYCopy SRAM byte on address YRx ← (Y)-2/3/41
LDRxY+Copy SRAM byte on address Y and increment addressRx ← (Y), Y = Y + 1-2/31
LDRx-YDecrement Y and copy SRAM byte at address YY = Y - 1, Rx ← (Y)-2/3/41
LDDRxY+KCopy SRAM byte from address (Y+K)Rx ← (Y+K)-2/3K: 0 to 631
LDRxZCopy SRAM byte from address ZRx ← (Z)-2/3/41
LDRxZ+Copy SRAM byte from address Z and increment addressRx ← (Z), Z = Z + 1-2/31
LDRx-ZDecrement Z and copy SRAM byte from address ZZ = Z - 1, Rx ← (Z)-2/3/41
LDDRxZ+KCopy SRAM byte from address (Z+K)Rx ← (Z+K)-2/3K: 0 to 631
STSARhCopy to SRAM(SRAM-A) ← Rx-2/3/4R: 16 to 312
STXRxCopy to SRAM address in X(X) ← Rx-2/3/41
STX+RxCopy to SRAM address in X and increment address(X) ← Rx, X = X + 1-2/31
ST-XRxDecrement X and copy to SRAM address XX = X - 1, (X) ← Rx-2/3/41
STYRxCopy to SRAM address Y(Y) ← Rx-2/3/41
STRxY+Copy to address Y and increment Y(Y) ← Rx, Y = Y + 1-2/31
STRx-YDecrement Y and copy to SRAM address YY = Y - 1, (Y) ← Rx-2/3/41
STDY+KRxCopy to SRAM address (Y+K)(Y+K) ← Rx-2/3K: 0 to 631
STZRxCopy to SRAM address Z(Z) ← Rx-2/3/41
STZ+RxCopy to SRAM address Z and increment Z(Z) ← Rx, Z = Z + 1-2/31
ST-ZRxDecrement Z and copy to SRAM address ZZ = Z - 1, (Z) ← Rx-2/3/41
STDZ+KRxCopy to SRAM address (Z+K)(Z+K) ← Rx-2/3K: 0 to 631
LPMCopy from program memory address (Z) to R0R0 ← (Flash Z)-31
LPMRxZCopy from program memory address (Z) to registerRx ← (Flash Z)-31
LPMRxZ+Copy from program memory address (Z) to register and increment ZRx ← (Flash Z), Z = Z + 1-31
ELPMCopy from extended program memory address (EIND+Z) to register R0R0 ← (Flash Z)-31
ELPMRxZCopy from extended program memory address (EIND+Z) to registerRx ← (Flash Z)-31
ELPMRxZ+Copy from extended program memory address (EIND+Z) to register and increment ZRx ← (Flash Z), Z = Z + 1-31
SPMCopy word R1:R0 to program memory address (Z)(Flash Z) ← R1:R0-N1
SPMZ+Copy word R1:R0 to program memory address (Z) and increment Z(Flash Z) ← R1:R0, Z = Z+ 1-N1
INRxPCopy port byteRx ← P-11
OUTPRxCopy byte to portP ← Rx-11
PUSHRxCopy to stack and dekrement (SP)(Stack) ← Rx, SP = SP - 1-21
POPRxCopy from stack and increment (SP)Rx ← (Stack), SP = SP + 1-21
XCHZRxExchange register with SRAM address (Z)Rx ↔ (Z)-11
LASZRxOR register and SRAM (Z) und exchangeRx ← Rx ODER (Z), (Z) ↔ Rx-11
LACZRxAND complement register with SRAM (Z) and copy to SRAM (Z)Rx ← (255-Rx) UND (Z), (Z) ↔ Rx-11
LATZ,RdXOR register and SRAM (Z) and exchangeRx EXOR (Z), Rx ↔ (Z)-11
Bit operations
LSLRxLogical shift leftRx ← Rx * 2Z,C,N,V,H11
LSRRxLogical shift rightRx ← Rx / 2Z,C,N,V11
ROLRxBinary rotate left with CRx ← Rx * 2 with Bit 0 = C/C = Bit 7Z,C,N,V,H11
RORRxBinary rotate right with CRx ← Rx / 2 with Bit 7 = C/C = Bit 0Z,C,N,V11
ASRRxArithmetical shift rightRx ← Rx(6:0) / 2, Bit 6 = 0 Z,C,N,V11
SWAPRxExchange upper and lower nibbleRx ← (7:4) ↔ (3:0)-11
BSETBSet bit in SREGSREG ← SREG OR (1<<B)-11
BCLRBClear bit in SREGSREG ← SREG AND (255-(1<<B))-11
SBIPLBSet bit in portPL ← PL OR (1<<B)-21
CBIPLBClear bit in portPL ← PL AND (255-(1<<B))-21
BSTRxBCopy register bit to TSREG-T ← Rx-Bit B-11
BLDRxBCopy T to register bitRx-Bit B ← T-11
SECSet SREG CSREG-Bit C ← 1-11
CLCClear SREG CSREG-Bit C ← 0-11
SENSet SREG NSREG-Bit N ← 1-11
CLNClear SREG NSREG-Bit N ← 0-11
SEZSet SREG ZSREG-Bit Z ← 1-11
CLZClear SREG ZSREG-Bit Z ← 0-11
SEISet SREG ISREG-Bit I ← 1-11
CLIClear SREG ISREG-Bit I ← 0-11
SESSet SREG SSREG-Bit S ← 1-11
CLSClear SREG SSREG-Bit S ← 0-11
SEVSet SREG VSREG-Bit V ← 1-11
CLVClear SREG VSREG-Bit V ← 0-11
SETSet SREG TSREG-Bit T ← 1-11
CLTClear SREG TSREG-Bit T ← 0-11
SEHSet SREG HSREG-Bit H ← 1-11
CLHClear SREG HSREG-Bit H ← 0-11
Controller instructions
BREAKStop execution, control to debugger-11
NOPDo nothing-11
SLEEPSleep-11
WDRClear watchdogWDR counter ← 0-11
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