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Applications => Audio level display
Audio level meter and display with an ATtiny24 and an LCD
A versatile meter for audio signals with high resolution (80 stages), high
sensitivity (full level from 19 mVeff upwards), very small
power consumption during operation (roughly 10 mA) and a broad range
This device measures audio signals and displays their level either in
logarithmic or linear manner as lighted band on an LCD in lines 3 (left
channel) and 4 (right channel). The maximum level is held for a preselected
time and is separately displayed.
Per second roughly four measure and display cycles are performed so that
the device is suited to display fast changing levels of audio signals.
The device uses the versatile internal opportunities that the internal
ADC in the ATtiny24 offers. In detail:
Other AVRs, escpecially those with an older design, such as the ATmega8(A)
or ATmega328(Px), do not offer those opportunities as they have single-ended
AD input only. Other types, such as the ATmega128A or ATtiny261A, offer
different gains (10, 100) and the encoding of those two-ended inputs are
different. Therefore the transfer of the software provided here to other
AVR types has to be handled with some care.
- the selection of the ADC reference voltage either derived from the
operating voltage (which is at 5 V because of the applied LCD)
or from a built-in constant voltage source of 1.1 V. This
increases sensitivity by roughly 4.
- several ADC input lines can be configured as differential amplifiers,
which work in front of the AD converter. With that the medium voltage
of the AF signal can be subtracted from the audio signal's level without
having to determine that separately. This eases the software
- the differential amplifiers can be configured with a gain of either 1
or 20. With that the sensitivity can be increased with a factor of 20.
External amplifiers for small signals are not necessary in most
Measuring AC signals
To measure AC with an Analog/Digital Converter its medium level has to
be increased, so that the whole input signal is zero or positive. This
can be achieved by modulating a voltage divider with the AC signal,
separated by an electrolytic capacitor. This capacitor separates the
DC from the AC input signal. The voltage divider with two identical
10 kΩ resistors divides the operating voltage of 5 V
by two. The electrolytic capacitor of 47 µF smoothes this
voltage so that the input signal has no influence on this voltage.
In this way the AC signal is increased by 2.5 V.
This increased signal voltage is fed, together with the medium voltage
to a differential amplifier (which is part of the ATtiny24). This
subtracts the medium voltage from the increased signal voltage and
feeds the difference to the ADC. The difference is negative for those
parts that are negative in the input signal. The ADC can either handle
negative voltages, if so configured, or it yields 0 as result, which
is chosen here.
With that, the ADC delivers values between 0 and 511, with the reference
voltage at 5 V.
With an ADC the input signal (here: 1,000 Hz) that can be measured correct
has to in between 0 V and the reference voltage (blue curve, Vpp
The differential amplifier in the ADC subtracts the medium voltage, if so
configured. If the negative input, in our case AIN3, is set to half the reference
voltage (= Uref / 2 = 0.55 resp. 2.5 V), the ADC measures
positive half waves only. The ADC can be configured to also measure negative
voltages, but this is not used here. Instead the results of the measurements
are multiplied by 2, so that this is compensated. The red line (2*Average)
In our case every 13,13 µs the AD measures that signal (ADC-Sense,
black points). With the maximum measurable AC signal applied, the average
is 362 (of the 1023 maximum that the ADC can measure).
Display of the level
The measured average value has to be converted to the number of columns that
are either fully or partially lighted on the LCD. This conversion can be done
in a linear or logarithmic form. The software decides that based on a parameter
that is defined within the head of the source code file. The lin curve is more
mathmatically oriented while the log curve is nearer to our own ear and sound
This diagram shows the dynamic range in dBu that is covered when logarithmic
conversion is chosen. dBu is defined as dBu = 20 * lg (Ueff / 0,755).
The gain of the differential amplifier (G) varies between 1 and 20, the
selected reference voltage between 1.1 and 5 V. This large range
should satisfy most needs and tastes.
If the linear conversion is selected the dynamic range is from
0,2 mVeff up to 2 Veff. This also offers a
wide opportunity for needs and tastes.
Those ranges are not very exact because of the following:
Corrections to the gain require a 16-by-16-bit multiplication. For most
of the practical applications this increase in accuracy is unnecessary,
so it was not implemented here.
- The subtracted medium voltage has to be exact half the reference
voltage, which is not exactly the case when simply using a voltage
divider with two 5% resistors. To get more exact results one should
measure the exact reference voltage (on the AREF pin) and apply half
of that to the AIN3 pin (e.g. with a ten turn adjustable resistor).
- The real gain of the differential amplifiers has to be measured to
get more exact results.
- The offset of the differential amplifier should be measured and the
measured results used to correct the ADC result.
The used LCD has 20 characters per line. To increase the display's
resolution the self-defined characters 0 to 3 are used. In the example
here the display of the levels 40 to 44 is shown.
To adjust AF levels a maximum display is necessary. This should cover a
longer period of signal strength measurements to be readable. In our case
the measured levels for 14 cycle periods are stored, which causes a delay
of roughly 3 seconds.
The display of this maximum uses the self-designed characters 4 to 7 of
the LCD. The picture shows, for a signal level of 44 units, the maximum
at 52 to 55.
The characters 0 to 7 were designed with the tool provided
This is the electronic scheme of the device. The measuring is performed
by the ATtiny24, the display is done with a 4 line and 20 character wide
The analog input signal is coupled in over a 1 µF electrolytic
capacitor to the AD inputs AIN1 (left channel) and AIN2 (right channel).
The voltage divider 12k/1.5k provides the medium voltage for the reference
voltage of 1.1 V, which is coupled via a 10k resistor to both AD
inputs and connected to AIN3. A 47 µF electrolytical capacitor
holds this medium voltage free of AC. The reference voltage of 1.1 V
is generated internally and blocked with a capacitor of 100 nF on the
The control pins RS, R/W and E of the LCD are attached to the port pins
PB0, PB1 and PB2. The upper four data bus bits of the LCD are attached
to the upper four port pins of port A. Communication on this bus is
bidirectional, R/W determines the direction. The LCD backlight is driven
by the current limiting resistor of 220 Ω, which provides a
small current of 7.7 mA.
To program the ATtiny24 within the target a six pin ISP plug is integrated.
This provides the signals MOSI, MISO, SCK and RESET for programming. MOSI,
MISO and SCK are also used for the LCD data bus. This does not conflict
because the data bus is not driven by the LCD during programming.
When programming the ATtiny24 the operating voltage can be selected as
reference voltage of the LCD. In this case the medium voltage has to be
adjusted to 2.5 V. This is done with the two resistors of
10 kΩ. With that the full signal amplitude of
5 Vpp = 1,77 Veff is covered. Other
components do not change.
This is the controller section of the mountings on a breadboard.
This is the mounting including the LCD and the 5 V supply part.
The software is in assembler and requires the following
adjustments prior to assembling.
; C O N S T A N T S T O A D J U S T
; Selection of operating modes
; Selection of the ADC reference voltage 1.1 or 5 V
.equ cAdc_1p1 = 1 ; 1 = 1.1 internal reference voltage
; 0 = Operating voltage as reference
; Selection of the differential gain 1 or 20
.equ cAdcGain = 20 ; ADC differential gain (1 or 20)
; Selection of operating modes Log or Lin
.equ cLog = 1 ; Logarithmic (1) or linear (0)
; Selection of the duration of holding the maximum
.equ cMaxHold = 14 ; 14 hold cycles for maximum
Other parameters can be selected by editing the source file. All
constants are checked prior to assembling, false entries lead to
error messages of the assembler. The assembler used has to be able
to process the directives .IF, .ELSE, .ENDIF und .ERROR "message".
ATMEL's Assembler2 and gavrasm are able to assemble that.
- cAdc_1p1 = 1 selects the internal voltage reference.
- cAdcGain = 20 selects the gain of the differential amplifier.
- cLog gibt an, dass die Anzeige logarithmisch erfolgen soll.
- cMaxHold = 14 selects the number of hold cycles for the
maximum calculation. A cyce is 0.217 s long, 14 corresponds
to 3 seconds.
The clock of the ATtiny24 is adjusted to 4 MHz by writing to the
CLKPR port. The default clock of 1 MHz is overwritten with that,
no fuses have to be changed.
Measuring is performed interrupt-driven with the ADC_RDY vector, the
controller is in the SLEEP mode idle. The service routine measures
the difference voltage on pins AIN1 and AIN2 one after the other.
The values are summed up in a 24 bit wide register, per channel.
If 8,192 measurements per channel have been performed, the T flag
in SREG is set and the calculation/display routine is executed.
There, the sums are divided by 4,096 (256 by ignoring the lowest
byte, by 16 through repeated LSR and ROR) and rounded. By comparing
the result with 80 defined levels in a flash table the number of
fully and partially filled characters is calculated. Fully filled
characters are defined by the LCD routine as 0, partially ones as
1 to 3.
To calculate the maximum level the resulting level of 0 to 79 is
written to a buffer after this buffer has been shifted upward by
one position. The buffer length controls the time over which the
maximum is held. From that buffer the maximum is calculated and
converted to the number of columns and to the displayed maximum
character 4, 5, 6 or 7. If the position where the maximum is to be
located is already occupied, the next higher column is selected and
the character 4 is displayed.
This is done for both channels (left and right) separately, the
result is assembled in a 2*20 character buffer in SRAM. These two
buffers finally are displayed in the lines 3 and 4 of the LCD.
The software is written in assembler and is
available here. To assemble
the source code the LCD include file is
required. Place both files into the same directory so that the
include file is found.
The devive works fine. The measured mV levels are differing from what
was measured with a voltmeter. The difference is mainly caused by the
unadjusted medium voltage. In most applications the difference is
This is a typical display with an audio signal on the right channel input.
Music levels can be displayed in a acceptable manner, as the video shows
(download the MPG version with sound, if your
browser does not display the video or if it has no sound).
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