Software for the led line with ATtiny13


;
; ****************************************************
; * Ledline Intensity control for LEDs with ATtiny13 *
; * Version 1 as of 24.03.2012                       *
; * (C)2012 by Gerhard Schmidt, avr-asm-tutorial.net *
; ****************************************************
;
; Include file for AVR type
.NOLIST
.INCLUDE "tn13def.inc" ; Header file for ATTINY13
.LIST
;
; ============================================
;   H A R D W A R E   I N F O R M A T I O N  
; ============================================
;
; Controls the intensity of two 12V-LED-lines
;
;               ____________
;              /  ATtiny13  |
;             |             |
;    RESET o--|RES       VCC|--o +5V VCC
;             |             |
; PotiA In o--|PB3       PB2|--o SCK
;             |             |
; PotiB In o--|PB4       PB1|--o MISO/OC0B
;             |             |
;      0 V o--|GND       PB0|--o MOSI/OC0A
;             |_____________|
;
; ============================================
;      P O R T S   A N D   P I N S 
; ============================================
;
.equ pba = PortB0
.equ pbb = PortB1
;
; =======================================
;  C O N S T A N T S   T O   A D J U S T
; =======================================
;
;
; =======================================================
;  F I X E D   A N D   D E R I V E D   C O N S T A N T S
; =======================================================
;
; Constant for starting the ADC
.equ cAdcStart = (1<<ADEN)|(1<<ADSC)|(1<<ADIE)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)
;
; ===========================================
;   R E G I S T E R   D E F I N I T I O N S
; ===========================================
;
; R0..R15 free
.def rmp = R16 ; Multipurpose register
.def rcnt = R17 ; Counter for AD-converter
.def radal = R18 ; LSB ADC results ADC3
.def radah = R19 ; dto., MSB
.def radbl = R20 ; LSB ADC results ADC4
.def radbh = R21 ; dto., MSB
; R22..R31 free
;
; ============================================
;       S R A M   D E F I N I T I O N S
; ============================================
;
.DSEG
.ORG  0X0060
;
; ==============================================
;   R E S E T   A N D   I N T   V E C T O R S
; ==============================================
;
.CSEG
.ORG $0000
 rjmp Main ; Reset-Vector
 reti ; Int0
 reti ; PcInt0
 reti ; TIM0_OVF
 reti ; EE_RDY
 reti ; ANA_COMP
 reti ; TIM0_COMPA
 reti ; TIM0_COMPB
 reti ; WDT
 rjmp IntAdc ; ADC
;
; ==========================================
;    I N T E R R U P T   S E R V I C E
; ==========================================
;
; ADC ready interrupt
IntAdc:
 brts IntAdcB ; T-flag set, B-Channel
 in rmp,ADCL ; read LSB result
 add radal,rmp ; add to result
 in rmp,ADCH ; read MSB result
 adc radah,rmp ; add to result
 dec rcnt ; decrement number of read cycles
 brne IntAdcRet ; not zero, go on
 ldi rcnt,64 ; restart cycle counter
 out OCR0B,radah ; set compare value B
 clr radal ; clear result value
 clr radah
 ldi rmp,1<<MUX1 ; select other channel
 out ADMUX,rmp
 set ; set flag for channel B
 rjmp IntAdcRet
IntAdcB:
 in rmp,ADCL ; read LSB result
 add radbl,rmp ; add to result
 in rmp,ADCH ; read MSB result
 adc radbh,rmp ; add to result
 dec rcnt ; decrease number of read cycles
 brne IntAdcRet ; not zero, go on
 ldi rcnt,64 ; restart cycle counter
 out OCR0A,radbh ; set compare value A
 clr radbl ; clear result value
 clr radbh
 ldi rmp,(1<<MUX1)|(1<<MUX0) ; select other channel
 out ADMUX,rmp
 clt ; set flag for channel B
IntAdcRet:
 ldi rmp,cAdcStart
 out ADCSRA,rmp ; restart AD converter
 reti
;
; ============================================
;    M A I N   P R O G R A M   I N I T
; ============================================
;
Main:
; Init stack
 ldi rmp, LOW(RAMEND) ; Init LSB stack
 out SPL,rmp
; Init Port B
 ldi rmp,(1<<pba)|(1<<pbb) ; Direction Port B
 out DDRB,rmp
; Init Timer
 ldi rmp,(1<<COM0A1)|(1<<COM0B1)|(1<<WGM01)|(1<<WGM00) ; Fast PWM
 out TCCR0A,rmp
 ldi rmp,(1<<CS01)|(1<<CS00) ; prescale by 64
 out TCCR0B,rmp
; Init ADC
 ldi rmp,(1<<ADC3D) ; disable digital input
 out DIDR0,rmp
 ldi rmp,(1<<MUX1)|(1<<MUX0) ; MUX to PB3
 out ADMUX,rmp
 ldi rmp,cAdcStart ; start ADC
 out ADCSRA,rmp
; Init sleep mode and ints
 ldi rmp,1<<SE ; Enable sleep
 out MCUCR,rmp
 sei
;
; ============================================
;          P R O G R A M   L O O P
; ============================================
;
Loop:
 sleep ; go to sleep
 nop ; Dummy for wakeup
 rjmp loop ; back to loop
;
; End source code
; Copyright
.db "(C)2012 by Gerhard Schmidt  " ; human readable
.db "C(2)10 2ybG reahdrS hcimtd  " ; wordwise
;