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Introduction to AVR assembler programming for beginners

The table of the relevant ports in the ATMEL AVR types AT90S2313, 2323 and 8515. Bytewise accessable ports or register pairs are not displayed in detail. No warranty for correctness, see the data sheets!

Status-Register, Accumulator flags

Port	Function	Port-Address	RAM-Address
SREG	Status Register Accumulator	0x3F	0x5F

7	6	5	4	3	2	1	0
I	T	H	S	V	N	Z	C

Bit	Name	Meaning	Opportunities	Conand
7	I	Global Interrupt Flag	0: Interrupts disabled	CLI
7	I	Global Interrupt Flag	1: Interrupts enabled	SEI
6	T	Bit storage	0: Stored bit is 0	CLT
6	T	Bit storage	1: Stored bit is 1	SET
5	H	Halfcarry-Flag	0: No halfcarry occured	CLH
5	H	Halfcarry-Flag	1: Halfcarry occured	SEH
4	S	Sign-Flag	0: Sign positive	CLS
4	S	Sign-Flag	1: Sign negative	SES
3	V	Two's complement-Flag	0: No carry occured	CLV
3	V	Two's complement-Flag	1: Carry occured	SEV
2	N	Negative-Flag	0: Result was not negative/smaller	CLN
2	N	Negative-Flag	1: Result was negative/smaller	SEN
1	Z	Zero-Flag	0: Result was not zero/unequal	CLZ
1	Z	Zero-Flag	1: Result was zero/equal	SEZ
0	C	Carry-Flag	0: No carry occured	CLC
0	C	Carry-Flag	1: Carry occured	SEC

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Stackpointer

Port	Function	Port-Address	RAM-Address
SPL/SPH	Stackpointer	003D/0x3E	0x5D/0x5E

Name	Meaning	Verfügbarkeit
SPL	Low-Byte of Stackpointer	From AT90S2313 upwards, not in 1200
SPH	High-Byte of Stackpointer	From AT90S8515 upwards, only in devices with >256 bytes internal SRAM

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SRAM and External Interrupt control

Port	Function	Port-Address	RAM-Address
MCUCR	MCU General Control Register	0x35	0x55

7	6	5	4	3	2	1	0
SRE	SRW	SE	SM	ISC11	ISC10	ISC01	ISC00

Bit	Name	Meaning	Opportunities
7	SRE	Ext.SRAM Enable	0=No external SRAM connected
7	SRE	Ext.SRAM Enable	1=External SRAM connected
6	SRW	Ext.SRAM Wait States	0=No extra wait state on external SRAM
6	SRW	Ext.SRAM Wait States	1=Additional wait state on external SRAM
5	SE	Sleep Enable	0=Ignore SLEEP commands
5	SE	Sleep Enable	1=SLEEP on command
4	SM	Sleep Mode	0=Idle Mode (Half sleep)
4	SM	Sleep Mode	1=Power Down Mode (Full sleep)
3	ISC11	Interrupt control Pin INT1 (connected to GIMSK)	00: Low-level initiates Interrupt
3	ISC11		01: Undefined
2	ISC10		10: Falling edge triggers interrupt
2	ISC10		11: Rising edge triggers interrupt
1	ISC01	Interrupt control Pin INT0 (connected to GIMSK)	00: Low-level initiates interrupt
1	ISC01		01: Undefined
0	ISC00		10: Falling edge triggers interrupt
0	ISC00		11: Rising edge triggers interrupt

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External Interrupt Control

Port	Function	Port-Address	RAM-Address
GIMSK	General Interrupt Maskregister	0x3B	0x5B

7	6	5	4	3	2	1	0
INT1	INT0	-	-	-	-	-	-

Bit	Name	Meaning	Opportunities
7	INT1	Interrupt by external pin INT1 (connected to mode in MCUCR)	0: External INT1 disabled
7	INT1	Interrupt by external pin INT1 (connected to mode in MCUCR)	1: External INT1 enabled
6	INT0	Interrupt by external Pin INT0 (connected to mode in MCUCR)	0: External INT0 disabled
6	INT0	Interrupt by external Pin INT0 (connected to mode in MCUCR)	1: External INT0 enabled
0...5	(Not used)

Port	Function	Port-Address	RAM-Address
GIFR	General Interrupt Flag Register	0x3A	0x5A

7	6	5	4	3	2	1	0
INTF1	INTF0	-	-	-	-	-	-

Bit	Name	Meaning	Opportunities
7	INTF1	Interrupt by external pin INT1 occured	Automatic clear by execution of the Int-Routine or Clear by command
6	INTF0	Interrupt by external pin INT0 occured
0...5	(Not used)

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Timer Interrupt Control

Port	Function	Port-Address	RAM-Address
TIMSK	Timer Interrupt Maskregister	0x39	0x59

7	6	5	4	3	2	1	0
TOIE1	OCIE1A	OCIE1B	-	TICIE1	-	TOIE0	-

Bit	Name	Meaning	Opportunities
7	TOIE1	Timer/Counter 1 Overflow-Interrupt	0: No Int at overflow
7	TOIE1	Timer/Counter 1 Overflow-Interrupt	1: Int at overflow
6	OCIE1A	Timer/Counter 1 Compare A Interrupt	0: No Int at equal A
6	OCIE1A	Timer/Counter 1 Compare A Interrupt	1: Int at equal A
5	OCIE1B	Timer/Counter 1 Compare B Interrupt	0: No Int at B
5	OCIE1B	Timer/Counter 1 Compare B Interrupt	1: Int at equal B
4	(Not used)
3	TICIE1	Timer/Counter 1 Capture Interrupt	0: No Int at Capture
3	TICIE1	Timer/Counter 1 Capture Interrupt	1: Int at Capture
2	(Not used)
1	TOIE0	Timer/Counter 0 Overflow-Interrupt	0: No Int at overflow
1	TOIE0	Timer/Counter 0 Overflow-Interrupt	1: Int at overflow
0	(Not used)

Port	Function	Port-Address	RAM-Address
TIFR	Timer Interrupt Flag Register	0x38	0x58

7	6	5	4	3	2	1	0
TOV1	OCF1A	OCF1B	-	ICF1	-	TOV0	-

Bit	Name	Meaning	Opportunities
7	TOV1	Timer/Counter 1 Overflow reached	Interrupt-Mode: Automatic Clear by execution of the Int-Routine OR Polling-Mode: Clear by command
6	OCF1A	Timer/Counter 1 Compare A reached
5	OCF1B	Timer/Counter 1 Compare B reached
4	(Not used)
3	ICF1	Timer/Counter 1 Capture-Event occured
2	(not used)
1	TOV0	Timer/Counter 0 Overflow occured
0	(not used)

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Timer/Counter 0

Port	Function	Port-Address	RAM-Address
TCCR0	Timer/Counter 0 Control Register	0x33	0x53

7	6	5	4	3	2	1	0
-	-	-	-	-	CS02	CS01	CS00

Bit	Name	Meaning	Opportunities
2..0	CS02..CS00	Timer Clock	000: Stop Timer
			001: Clock = Chip clock
			010: Clock = Chip clock / 8
			011: Clock = Chip clock / 64
			100: Clock = Chip clock / 256
			101: Clock = Chip clock / 1024
			110: Clock = falling edge of external Pin T0
			111: Clock = rising edge of external Pin T0
3..7	(not used)

Port	Function	Port-Address	RAM-Address
TCNT0	Timer/Counter 0 count register	0x32	0x52

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Timer/Counter 1

Port	Function	Port-Address	RAM-Address
TCCR1A	Timer/Counter 1 Control Register A	0x2F	0x4F

7	6	5	4	3	2	1	0
COM1A1	COM1A0	COM1B1	COM1B0	-	-	PWM11	PWM10

Bit	Name	Meaning	Opportunities
7	COM1A1	Compare Output A	00: OC1A/B not connected 01: OC1A/B changes polarity 10: OC1A/B to zero 11: OC1A/B to one
6	COM1A0	Compare Output A
5	COM1B1	Compare Output B
4	COM1B0	Compare Output B
3	(not used)
2	(not used)
1..0	PWM11 PWM10	Pulse width modulator	00: PWM off 01: 8-Bit PWM 10: 9-Bit PWM 11: 10-Bit PWM

Port	Function	Port-Address	RAM-Address
TCCR1B	Timer/Counter 1 Control Register B	0x2E	0x4E

7	6	5	4	3	2	1	0
ICNC1	ICES1	-	-	CTC1	CS12	CS11	CS10

Bit	Name	Meaning	Opportunities
7	ICNC1	Noise Canceler on ICP-Pin	0: disabled, first edge starts sampling
7	ICNC1	Noise Canceler on ICP-Pin	1: enabled, min four clock cycles
6	ICES1	Edge selection on Capture	0: falling edge triggers Capture
6	ICES1	Edge selection on Capture	1: rising edge triggers Capture
5..4	(not used)
3	CTC1	Clear at Compare Match A	1: Counter set to zero if equal
2..0	CS12..CS10	Clock select	000: Counter stopped 001: Clock 010: Clock / 8 011: Clock / 64 100: Clock / 256 101: Clock / 1024 110: falling edge external Pin T1 111: rising edge external Pin T1

Port	Function	Port-Address	RAM-Address
TCNT1L/H	Timer/Counter 1 count register	0x2C/0x2D	0x4C/0x4D

Port	Function	Port-Address	RAM-Address
OCR1AL/H	Timer/Counter 1 Output Compare register A	0x2A/0x2B	0x4A/0x4B hex

Port	Function	Port-Address	RAM-Address
OCR1BL/H	Timer/Counter 1 Output Compare register B	0x28/0x29	0x48/0x49

Port	Function	Port-Address	RAM-Address
ICR1L/H	Timer/Counter 1 Input Capture Register	0x24/0x25	0x44/0x45

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Watchdog-Timer

Port	Function	Port-Address	RAM-Address
WDTCR	Watchdog Timer Control Register	0x21	0x41

7	6	5	4	3	2	1	0
-	-	-	WDTOE	WDE	WDP2	WDP1	WDP0

Bit	Name	Meaning	WDT-cycle at 5.0 Volt
7..5	(not used)
4	WDTOE	Watchdog Turnoff Enable	Previous set to disabling of WDE required
3	WDE	Watchdog Enable	1: Watchdog aktive
2..0	WDP2..WDP0	Watchdog Timer Prescaler	000: 15 ms 001: 30 ms 010: 60 ms 011: 120 ms 100: 240 ms 101: 490 ms 110: 970 ms 111: 1,9 s

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EEPROM

Port	Function	Port-Address	RAM-Address
EEARL/H	EEPROM Address Register	0x1E/0x1F	0x3E/0x3F

EEARH only in types with more than 256 Bytes EEPROM (from AT90S8515 upwards)

Port	Function	Port-Address	RAM-Address
EEDR	EEPROM Data Register	0x1D	0x3D

Port	Function	Port-Address	RAM-Address
EECR	EEPROM Control Register	0x1C	0x3C

7	6	5	4	3	2	1	0
-	-	-	-	-	EEMWE	EEWE	EERE

Bit	Name	Meaning	Function
7..3	(not used)
2	EEMWE	EEPROM Master Write Enable	Previous set enables write cycle
1	EEWE	EEPROM Write Enable	Set to initiate write
0	EERE	EEPROM Read Enable	Set initiates read

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Serial Peripheral Interface SPI

Port	Function	Port-Address	RAM-Address
SPCR	SPI Control Register	0x0D	0x2D

7	6	5	4	3	2	1	0
SPIE	SPE	DORD	MSTR	CPOL	CPHA	SPR1	SPR0

Bit	Name	Meaning	Function
7	SPIE	SPI Interrupt Enable	0: Interrupts disabled
7	SPIE	SPI Interrupt Enable	1: Interrupts enabled
6	SPE	SPI Enable	0: SPI disabled
6	SPE	SPI Enable	1: SPI enabled
5	DORD	Data Order	0: MSB first
5	DORD	Data Order	1: LSB first
4	MSTR	Master/Slave Select	0: Slave
4	MSTR	Master/Slave Select	1: Master
3	CPOL	Clock Polarity	0: Positive Clock Phase
3	CPOL	Clock Polarity	1: Negative Clock Phase
2	CPHA	Clock Phase	0: Sampling at beginning of Clock Phase
2	CPHA	Clock Phase	1: Sampling at end of Clock Phase
1	SPR1	SCK clock frequency	00: Clock / 4
1	SPR1		01: Clock / 16
0	SPR0		10: Clock / 64
0	SPR0		11: Clock / 128

Port	Function	Port-Address	RAM-Address
SPSR	SPI Status Register	0x0E	0x2E

7	6	5	4	3	2	1	0
SPIF	WCOL	-	-	-	-	-	-

Bit	Name	Meaning	Function
7	SPIF	SPI Interrupt Flag	Interrupt request
6	WCOL	Write Collision Flag	Write collission occured
5..0	(not used)

Port	Function	Port-Address	RAM-Address
SPDR	SPI Data Register	0x0F	0x2F

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UART

Port	Function	Port-Address	RAM-Address
UDR	UART I/O Data Register	0x0C	0x2C

Port	Function	Port-Address	RAM-Address
USR	UART Status Register	0x0B	0x2B

7	6	5	4	3	2	1	0
RXC	TXC	UDRE	FE	OR	-	-	-

Bit	Name	Meaning	Function
7	RXC	UART Receive Complete	1: Char received
6	TXC	UART Transmit Complete	1: Shift register empty
5	UDRE	UART Data Register Empty	1: Transmit register available
4	FE	Framing Error	1: Illegal Stop-Bit
3	OR	Overrun	1: Lost char
2..0	(not used)

Port	Function	Port-Address	RAM-Address
UCR	UART Control Register	0x0A	0x2A

7	6	5	4	3	2	1	0
RXCIE	TXCIE	UDRIE	RXEN	TXEN	CHR9	RXB8	TXB8

Bit	Name	Meaning	Function
7	RXCIE	RX Complete Interrupt Enable	1: Interrupt on received char
6	TXCIE	TX Complete Interrupt Enable	1: Interrupt at transmit complete
5	UDRIE	Data Register Empty Interrupt Enable	1: Interrupt on transmit buffer empty
4	RXEN	Receiver Enabled	1: Receiver enabled
3	TXEN	Transmitter Enable	1: Transmitter enabled
2	CHR9	9-bit Characters	1: Char length 9 Bit
1	RXB8	Receive Data Bit 8	9th Data bit on receive
0	TXB8	Transmit Data Bit 8	9.Data bit on transmit

Port	Function	Port-Address	RAM-Address
UBRR	UART Baud Rate Register	0x09	0x29

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Analog Comparator

Port	Function	Port-Address	RAM-Address
ACSR	Analog Comparator Control and Status Register	0x08	0x28

7	6	5	4	3	2	1	0
ACD	-	ACO	ACI	ACIE	ACIC	ACIS1	ACIS0

Bit	Name	Meaning	Function
7	ACD	Disable	Disable Comparators
6	(not used)
5	ACO	Comparator Output	Read: Output of the Comparators
4	ACI	Interrupt Flag	1: Interrupt request
3	ACIE	Interrupt Enable	1: Interrupts enabled
2	ACIC	Input Capture Enable	1: Connect to Timer 1 Capture
1	ACIS1	Input Capture Enable	00: Interrupt on edge change
1	ACIS1		01: not used)
0	ACIS0		10: Interrupt on falling edge
0	ACIS0		11: Interrupt on rising edge

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I/O Ports

Port	Register	Function	Port-Address	RAM-Address
A	PORTA	Data Register	0x1B	0x3B
	DDRA	Data Direction Register	0x1A	0x3A
	PINA	Input Pins Address	0x19	0x39
B	PORTB	Data Register	0x18	0x38
	DDRB	Data Direction Register	0x17	0x37
	PINB	Input Pins Address	0x16	0x36
C	PORTC	Data Register	0x15	0x35
	DDRC	Data Direction Register	0x14	0x34
	PINC	Input Pins Address	0x13	0x33
D	PORTD	Data Register	0x12	0x32
	DDRD	Data Direction Register	0x11	0x31
	PIND	Input Pins Address	0x10	0x30