The ATmega8 is clocked with a 2.048 MHz xtal. With
small changes of the software, xtals with 2.0 or 8.0 MHz
can also be used.
Power supply is with four 1.2 V rechargeable batteries
so that standard LCDs with 5 V operating voltage can
The four-by-twenty LCD is connected to an 8 bit bus and three
control pins at the ATmega8 (including Read/Write). By default
the LCD is controlled in busy flag mode, but switching to
wait mode is possible with a slight change of the source code.
One key clears the stopwatch, one key starts and stops the
watch and four keys (or low-active sensors) stop the four
The ISP interface allows programming of the controller within
the running system.
2 Software structure
2.1 Display scheme
The display organization is shown here. It shows the display
during running time measurement, and
after having stopped two of the four channels.
2.2 Clock options
The millisecond clock is derived from the Xtal frequency
as follows. When using a 2.0 or 8.0 MHz Xtal the
8 bit timer TC2 generates the ms clock via CTC mode and
Compare Match A interrupt. If the default 2.048 MHz
Xtal is used, this timer runs in free running mode and
generates the 1 ms with the overflow interrupt.
At 2.0 and 2.048 MHz the 8 bit timer TC2 works with
a prescaler of 8, if a 8.0 MHz Xtal is used the
prescaler is at 64.
2.3 Interrupt Service Routine TC2
The Interrupt Service Routine of TC2, either triggered
by the TC2OVF or by the TC2CMP vector, first reads in
the current state of the keys. Handling of the keys
is done outside the ISR, triggered by the bmS flag.
Then the bRun flag is checked if the time measurement
is on. If yes the millisecond counter is increased. If
that counter reaches 100, it is resetted and the bdS
flag is set. Further time counting is done outside the
2.4 Handling of the millisecond flag
With the millisecond flag set, all keys are checked and,
if active, the different actions are taken.
Firstly, the ms flag is cleared to enable her re-setting
within the ISR's next cycle.
If the Reset key is pressed (input pin is low),
the following happens:
the bRun flag is cleared, by that stopping the
the time registers are cleared,
all channel flags are cleared,
all LCD lines display zero, and.
further key processing is skipped.
The Start/Stop key requires debouncing to avoid
short pulses of the key. To do that a debouncer
register called rTgl is set to a predefined number
of counts. In case of an inactive Start/Stop key this
register is counted down each millisecond. Only if
that register is zero, an active pulse is accepted
and the bRun flag is reversed. After each active
pulse at the key input, be it succesful or not,
restarts this counter with the constant cTgl. cTgl
should be large enough to cover usual bouncing
times of keys (several tens of microseconds).
Following Start/Stop key processing the four channel
inputs are checked. First it is checked if the
time is zero, for which it makes no sense to stop
channels. If larger than zero, all channels are
checked whether the respective key is pressed
and the channel is still running (channel bit in
rFlag = 0). If that is the case, the channel is
stopped (by setting its flag bit),
the current time is written to the SRAM
storage place of this channel,
the channel number is stored in the stop
row in the SRAM, and
this time is displayed at the LCD line of
If all four channels have been processed it is
checked whether all four channels are stopped.
If that is the case, the stop row list in SRAM
is used to display a sorted list of channels
with increasing times.
2.5 Deciseconds handling
The bdS flag signals that 100 microseconds are
over and that the deciseconds (and, if necessary,
the rest of the clock registers) need an update.
The flag is cleared and the time is increased.
In all channels that not yet have been stopped
(channel flag = 0), the current time is
displayed (hours, minutes, seconds and
deciseconds, but not the milliseconds).
2.6 Tone generation
The tone generation is performed with the 16 bit
timer TC1 in CTC mode and clocked with a prescaler
of 8. At 2.0 MHz clock tones between
3.8 Hz and 250 kHz can be played, at
8.0 MHz clock between 15.3 Hz and
1 MHz are possible.
Tone output is on output pin OC1A, which is toggled
on compare match if tones are on and cleared if
tones are off. This unloads the capacitor on the
OC1A output so that no current can flow into the
pin when the operating voltage drops.
On each compare match an interrupt is triggered.
The ISR counts down the 16 bit counter in R25:R24.
If the counter reaches zero, the OC1A mode is
changed to clear, switching tone output off
in the next count cycle. Therefore R25:R24 controls
the duration of the tones.
The tone frequencies and the duration of the tones
is defined in the constants cTonexxx (in Hz) and
cTonexxxDur (in ms). From these constants the
Compare values cCmpXXX for the TC1-CTC and the
values cCtrXXX for the tone duration counter are
calculated and listed in a table called
ToneTable: (duration word first, compare
value word second).
The routine ToneStart: starts the tone,
for which its number (0..10) is in register rmp.
First the counter value is read and set, then the
For the tones different octaves have been selected.
During power-up and for the keys Reset and Start/Stop
the fourth octave was selected, seconds/minutes/hours
are one octave lower and the four channel keys are
by two octaves lower. Other combinations and tones
can be selected by changing the constants in the
2.7 LED control
LED control is done with the portpin PB2. During
init the LED is permanently on. When time measurement
is active the LED is blinking in tenth of seconds
for the four active channels (counting channels
are on), followed by an off-period of four tenth
of seconds. When all four channels are stopped
the LED is permanently off.
2.8 Sorting by minimum times
If all four channels are stopped, the four times
are displayed in a sorted list by minimum time.
The row, in which the four channels were stopped,
is stored in SRAM. The four times are either stored
If during assembling the switch eep was set to
1 all twenty data bytes for times and the four row bytes
are written to EEPROM. The EEPROM content can be read.
The assembler source code for the stopwatch with an ATmega8
can be downloaded from
here and viewed in the
For assembling the LCD include file
lcd.inc is required which provides
all LCD routines.
The software is by default configured as follows:
Xtal frequency: 2.048 MHz, clock = 2048000
LCD 4x20 8 bit data bus in busy mode
EEPROM write off
When programming the chip its fuses have to be changed
to a medium-speed crystal (2.0 or 2.048 MHz) or a
high-speed crystal (8.0 MHz), otherwise the measured
times and the tones played are not correct.
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