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DCF77 AM direct receiver with a regulated OpAmp and a ATtiny25
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This project is experimental. I don't know if it really works as planned here.

10 DCF77 AM direct receiver with gain-regulated OpAmp and ATtiny25

DCF direct receivers need a regulated gain amplifier. The reasons for that are that
  1. the information in the DCF77 signal is encoded in the amplitude, so amplification must now be too high to avoid amplitude clipping,
  2. too high amplification leads to self-oscillation of the amplifier. At necessary gains of 5,000 and higher this is an issue.
This concept here uses The output of the ATtiny25 on the two pins 3 and 7 can be configured as follows:
  1. no signal, both pins remain low, or
  2. original DCF77 signal on pin 3, inverted DCF77 signal on pin 7, no change in the signal, or
  3. original DCF77 signal on pin 3 every second, followed by a short clock signal on pin 7, on minute change a long clock signal on pin 7, or
  4. on each minute transmission of all 59 original DCF77 bits in a row with a programmable clock speed and with data bits on pin 3 and clock on pin 7, or
  5. decoded time transmitted as serial ASCII each minute, in the format "T14:59" as derived from the decoded DCF77 signal, or
  6. decoded time and date as serial ASCII each minute, in the format "T14:59D20.12.14WMo".
Conversion of the ME(S)T time to UTC can be configured within the software.

10.0 Index

  1. Hardware
    1. Hardware schematic
    2. How the antenna circuit works
    3. How the regulated OpAmp works
    4. Generation of the negative gain control voltage
    5. The AFC control via the OC0A-PWM
  2. Software
    1. Software download
    2. Software overview
    3. The AD conversion of the input signal
    4. The AGC control via the OCR0B-PWM
    5. The AFC scan at start-up
    6. The AFC under normal circumstances
    7. Analyzing the DCF77 signal
    8. Converting the DCF77 bits to date and time
    9. Transmitting the status and results

10.1 Hardware of the regulated OpAmp receiver

10.1.1 Receiver hardware schematic

Schematic of the regulated OpAmp receiver This is all you need: The analog signal then is transferred to the controller's ADC3 input pin (see below).

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10.1.2 How the antenna circuit works

1 mH ferrite coil The 1 mH ferrite coil has been made from a 10-cm ferrite rod, which was covered over its hole length with two to three layers of adhesive tape, on which a coil with 0.25 mm copper wire was twisted. To find out how many windings would be necessary for 1 mH I stopped at 100, 130 and 160 windings and measured the inductivity. With these values I determined the specific inductivity per winding2 AL. These values are shown in the table.

WindingsInductivity [mH]AL [nH per w2]
1000.4039.72
1300.7544.56
1601.0540.88


The AL value, therefore, is roughly 41 nH/winding2. For a 2 mH coil roughly 220 windings would have been necessary.

Ohm's resistance of the 160 windings is 5.6 Ω, inductive resistance at 77.5 kHz is 510 Ω. The C needed for resonance at 77.5 kHz is 4.03 nF.Preferred Styroflex capacitors of 3.3 nF are in the market, so with the three varactor diodes at 243 pF the resonance can be reached. A 3.9 Styroflex would also be fine, but the varactors would then be very small in capacity.

The LC ciruit's resistance, when L and C are in resonance at 77.5 kHz, is around 50 kΩ or higher. So usual transistor or OpAmp stages are not recommendable, the OpAmp should have a FET on the input.

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10.1.3 How the regulated OpAmp works

OpAmp amplifier with fixed gain OpAmp amplifier with variable gain In the original design displayed here I tried to replace the resistor R1 in a linear amplifier stage with a FET. Its gate voltage can be varied between zero and minus 4.6 V. That varies the resistance of the Drain-to-Source pins of the FET between some 100 Ω and up to more than 1 MΩ.

RDSon excerpt from datasheet of the BF245 This shows the variation of RDSon of the three BF245 FETs. The curve starts at roughly 200 Ω (for a BF245A) or less and, with rising negative voltages on the gate pin, rises to more than 100 kΩ. The BF245C needs higher negative voltages than the A or B type for the same RDSon.

RDSon and achievable gain of the BF256B FET This type of diagram is not available for other JFETs. Usually only IDSS is listed, which is the current through the Drain-Source, with the gate at 0 V and at a certain voltage (mostly 15 V) on the drain. This is useful for calculating RDSon at 0 Volt, but yields too high and unrealistic resistances (the 15 V are unrealistic). Therefore I have measured a BF246B by adding a resistor on the drain and measuring the drain's voltage at different gate voltages. The diagram shows for the limited number of measurements that the current through the drain yields realistic RDSon values (in red) and that the calculated OpAmp gain is between one and 10,000.

A gain of 10,000 means that an amplitude of 0.1 mV HF is amplified to 1 V on the output. So, the gain is sufficient for the DCF77 signal in Germany. In larger distance additional amplification is necessary, e. g. adding another CA3140, regulating it with another FET and the same AGC voltage. If the amplification is too high then, make the 1 MΩ smaller. As the amplifier is in both cases linear (= is not inverted), self-oscillation by feedback from the output to the entry is less probable.

Unlike than in theory, this concept does not work properly: the CA3140 does not amplify at all with this setting. The only way to get the CA3140 to work was to shift its offset voltage extremely to one side. I used a 4k7 trim resistor, conncted this to pins 1 and 5 and the middle to GND. If the trim resistor is roughly at four fifth of its capacity the CA3140 starts to work and amplify. But when increasing the offset voltage a little bit further, the CA3140 starts wild swings, even with a gain of only 10 or 100. The stable area is even depending from the varactor's voltage on the LC circuit. I dropped this concept as it is too unreliable.

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10.2 The controller ATtiny25

The ATtiny25 controller No receiver without an AVR controller. This here has the following tasks:
  1. It produces the AFC voltage. This uses the OCR0A PWM channel to generate a RC filtered DC to control the frequency of the receiver's LC ciruit.
  2. It controls the gain. For that the OCR0B channel produces a rectangle that is rectified to produce a negative voltage for the FET. The channel is switched on, if the signal strength ois too small, and it is switched off when the signal strength is too high.
  3. All the analysis of the DCF77 signal is also done by the ATtiny25: it detects zeroes and ones transmitted and it detects minute changes. The results of the analysis are reflected on the clock and data signal, which is configurable by the source code: it can simply follow DCF77's signal (normal and inverted), it can transmit the time received in sync or in async serial format, or it can transmit date and time in both formats with selectable baud rates.
The two pins PB2 and PB4 produce the output signal. Depending from the switches in the source code, one of above described output modes are possible.

10.2.1 Generation of the negative gain control voltage

AGC voltage generator Response of the RC filter network on the gate of the FET The generation of the negative control voltage for the gate of the FET (AGC) is done with a coil, two capacitors of 470 nF and two Germanium-Diodes. If OC0B produces a rectangle, this generator delivers -4.6 V, if permanently on. This is enough for all types of FET (A to C types). Driving the OCR0B-PWM output with other OC0B compare values than 0x7F has nearly no effect, the control voltage has to be regulated by switching the output pin OC0B off and on, the long time constant of 1 MΩ * 100 µF is long enough to not change control voltages too fast, e. g. when DCF77 is reducing its amplitude to transmit a zero (100 ms) or a one (200 ms), and to smooth the signal during pump phases (when full, the AC on that 100 µF capacitor is at less than 1 mV).

On more details on the algorithm that controls the AGC voltage see the software section below.

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10.2.2 The AFC control via the OC0A-PWM

OC0A as AFC controller The OC0A PWM for the Automatic frequency control The OC0A-PWM produces an 8-bit-PWM signal that is filtered with a three-stage RC network. The filtered signal is then applied as control voltage for the three varactor diodes that control the frequency of the input ferrite coil and the resonant circuit. As there are no other components than this circuit, it is of special interest to tune this to exactly 77.5 kHz.

The three stages are necessary to reduce the PWM noise. In the first stage (yellow band) the noise is still around 200 mVpp (see the calculation sheet opampreg_OC0A in the LibreOffice calc file here. Already in the second stage (red) this drops down to 6 mVpp. Finally, in the third stage (blue), it is below 1 mVpp, small enough to operate the varactor diodes with: a ripple of +/-1 mVpp here corresponds to a frequency deviation in the LC entry stage of +/-5 Hz.

In the start-up phase the PWM value of the OC0A is scanned. The scan starts at 255, which is reduced by 8 in each scan step (-0.16 V per step). The long-term maximum and the long-term average over more than 2 seconds are determined and the maximum difference between maximum and average is searched for. During the more than 2 second long averaging at least one amplitude drop occurs at DCF77, so the average drops. The PWM value of the highest difference is used as start value for the AFC-PWM on finishing the scan.

During normal operation the AFC value is varied by one, which corresponds to voltage changes of 0.02 V. In a first measurement the difference between the long-term maximum and the long-term average are determined. The PWM value is then decreased by one and the difference is measured again. After that the PWM value is increased by two and the third difference measurement is made. The maximum of the three measurements is used to adjust the PWM value. See the software section below for details on the algorithm.

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10.2.3 Transmission of status and results

Pins 3 and 7 of the ATtiny25 can be configured as out- and inputs by setting cTxMode before assembling the source code:
  1. Both pins are output, both are low, no signals are transmitted, or
  2. Both pins are output, pin 3 follows the DCF77 signal's amplitude, pin 7 reverses the signal on pin 3 (inverted DCF77 amplitude signal), or
  3. Both pins are output, pin 3 transmits the content in sync serial mode as given with the baud rate setting in cTxBaud, pin 7 goes high after one third of the bit's duration and remains high over one third, then goes low for the third phase (strobe), the picture shows the transmission of one character via the two-wire interface:

    Bit transmission in sync mode

    The signal's polarity (true or inverted) can be selected by software. Or
  4. pin 3 is async serial output, pin 7 is input. If pin 7 is high (Clear-To-Send) the status and data to be transmitted is send bytewise in async mode with one start-bit and two stop-bits (8N2) with the selected baud-rate in cTxBaud. The first picture shows the transmission of the eight bits of one character over the RS232 lines, the second one the respective signals on pin 3 of the ATtiny25:

    Bit transmission in async mode

    The interface to transfer these bits over a standard RS232 interface is shown here:

    Interfacing the receiver to an RS232

    . With this interface the signal polarity has to be reversed by setting the appropriate constant in the source code, because the MAX232 is inverting the signals.
The constant cTxContent selects which informations are transmitted. See the software section for more details.

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10.3 The software

10.3.1 Software download

The software is still under construction. $$To be done$$

10.3.2 Software overview

The software has to do the following:
  1. to measure the incoming signal with ADC3 and to find its maximum and average over a certain period, and
  2. from the maximum signal strength: to determine if the negative gate voltage has to be increased (if the maximum of the signal strenth exceeds a certain programmed limit, e.g. +2.5 V), in which case the PWM output pin is switched active, toggles with 50% pulse width and by that increases the negative voltage on the FET's gate and reduces the OpAmp's gain, and
  3. if no gain adjustment had been made and if no low-phase of the DCF77 signal is active, the AFC-PWM is measured at one lower position and at one higher position of the PWM, the difference between tha maximum and the average signal strength is analyzed to adjust the AFC-PWM to higher values, and
  4. if during a high period of DCF77, it is checked whether the maximum falls below the average, the number of such cases is counted, if it reaches three, a low period of DCF77 is recognized and the low period counter is restarted, and
  5. if during a low period of DCF77, it is checked whether the maximum is larger than the average, if that is the case and the low counter reaches three, the low period ends and the high period starts, and
  6. when in a high period of DCF77 a transition to low is recognized, it is checked whether the duration of the high period was within the bounds of a minute change duration, if that is the case, the minute change is transmitted (if the output mode is larger than 1), the number of received bits is cleared (if the output mode is larger than 2), the decoding of the bits is started and transmission is started (if output mode is larger than 3), and
  7. when in a low period of DCF77 a transition to high occurs, the duration of the low period is converted to a zero or a one and shifted into the DCF77-bit-buffer, and
  8. if any of the output modes is set, either
    1. the low-to-high and the high-to-low transistions are reflected on the pins 3 (non-inverted) and 7 (inverted) (Mode 1), or
    2. the high-to-low transition is followed by a longer pause on pin 7 (Mode 2), or
    3. if a minute change occurs, all 59 DCF77 bits are send, either in synchronous mode over pin 3 (data) and pin 7 (clock) or in asynchronous mode over pin 3, or
    4. the DCF77 signals are converted to a time string, either in ME(S)T or as UTC, and the time string is send, either in synchronous or in asynchronous mode, or
    5. all DCF77 bits are converted to a time/date string, either in ME(S)T or as UTC, and the time/date string is send, either in synchronous or in asynchronous mode,
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10.3.3 The AD conversion of the input signal

The AD conversion of the input signal determines the whole timing of the software. This is done by running the ADC in free-running mode (auto-start of the conversion on completion), by clocking the ADC as fast as possible and by use of interrupts.

As the high-resolution 10-bit ADC result is not necessary here, the ADLAR bit is set and only the MSB is read.

As the detection of the maximum of the input signal and the averaging has to be done inside the interrupt service routine to achieve a reliable result and timing, the ISR routine lasts between 32 and 37 clock cycles. As this would be too long for a 1 MHz clock, the ATtiny's clock rate is set to 4 MHz by use of the CLKPR portregister at the very beginning. The ADC prescaler is set to 4. If each conversion needs 14 clock cycles, the ADC is running with 71.43 kHz and needs 14 µs per conversion. At 4 MHz clock, that provides 56 clock cycles for the Interrupt Service Routine, enough time to absolve the routine.

One specialty has to be considered in free-running mode: the next conversion is not already started when the last has finished. It is started when the previous conversion result has been read. As this lasts 8 clock cycles (ADC interrupt plus one ADCH read cycle), the restart of the ADC is slightly delayed and a bit more than 14 clock cycles are necessary.

ADC measurments With that timing, the DCF77 signal is sampled close to once per wave. As with a max count of 256 ca. 707 DCF77 waves are sampled. This is modelled in the calculation sheet opampreg_maxdetection in the LibreOffice file here. In this simulation the amplitude readings were calculated with 20% random jitter, to have it more realistic. Here, 340 DCF waves were simulated (see All values), every twentieth was measured (see measured values). As the sheet shows, the maximum detection and the average calculation is rather accurate, when the calculated maxima over 340 measurements and the calculated averages over 256 measurements are compared to the ideal values calculated in All values.

Another modification was made in the software: only ADC values that are not zero are tested for the maximum and are added to the average. That is correct as the OpAmp output only has positive voltage swings and is zero while the input is in the negative swing. That increases the number of measurements by two, so that 2 * 340 (for the maximum) and 2 * 256 samples (for the average) are collected. The calculation sheet considers only 340, so is conservative.

To count to 640, the 16-bit counter in R25:R24 is used solely for that purpose.

Differently calculated is the average: Here, 256 measuring results are collected, all zeroes are not counted and only the sum's MSB of those measurements is later used as average. This provides an average value over 2 * 256 / 70.2 = 7.29 ms time. As this average value is used to determine whether DCF is currently transmitting a zero or a one, by comparing it with a long-term average.

Two different maxima and average values are calculated:
  1. the short-term maximum and average values over 9.1 or 7.3 ms, and
  2. the long-term maximum and average values over 2.3 or 1.87 seconds.
Both long-term values add 256 single values up and take only the MSB.

The long-term maximum value is not used, because the AGC is derived from the short-term maximum. The long-term average is used to detect a zero/one DCF transmission: if the short-term average falls below the long-term average, a zero/one transmission starts. The software needs three of these signals to detect such a zero/one. The same happens if the short-term average is for at least three times higher than the long-term average: the end of a zero/one phase happens. The time over which both events happened determines if a zero or a one has been transmitted.

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10.3.4 The AGC control via the OCR0B-PWM

If the amplitude, as measured by the ADC on the ADC3 input pin, is too high (the compare value can be selected by setting a constant in the source code), the OC0B PWM is switched off. This is done by clearing the COM0B1 bit: the PWM is still running but the output pin OC0A is not toggled any more. Therefore the oscillator is really switched off and does not feed negative voltages further on.

When switching the OC0B signal off, the 100µF unloads via the 1 MΩ resistor. This curve is smoother, so more than 15 seconds are needed to increase the gain of the OpAmp again to more than 1,000. This ensures that the gain can be regulated by switching the generator on and off in a sensitive manner, and even the voltage drops of the DCF77 signal during transmissions of zeros and ones do not dramatically affect the RC-averaged gain of the OpAmp.

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10.3.5 The AFC scan at start-up

Flow chart of the scanning phase Because there can be other transmitters than DCF77 in the tune-able range, at least some interferers come into consideration:
  1. First of all: the fifth harmonic of the 15.625 kHz PWM is at 78.125 kHz, only 625 Hz away from our desired 77.5 kHz signal, so hold the connections short and the antenna far away from the PWM controller.
  2. Near my location here near Frankfurt/Germany I have a strong signal at 80 kHz. I don't know where this comes from.
  3. My energy-saving lamp transmits at 70 kHz as well.
Therefore the simple maximum of the signal strength is not an appropriate criteria for finding the optimal AFC voltage: the AFC would lock into these strongest signals, that aren't DCF77. It is the amplitude drop of DCF77 that allows to tune in exactly to that frequency. Therefore, to detect the best of the measuring points, the difference between the measured maximum and the average over 256 measurements of those is used. This difference, which has at least one zero/one drop of DCF's amplitude, is a much more reliable criterion.

At the beginning, the PWM starts with 255 (= 5 V) and, in a raw run, decreases the PWM value by 8 and down to 47 (= 0.9375 V). To determine the wait time until the changed voltage follows within the RC network, the calculation shown on the graph here starts with a compare value of 128 at 2.5 V. Shortly after 0.5 seconds the PWM value drops by 8 (down to 2.1875 V). As can be seen, it takes roughly 1.5 seconds to come near the changed target value and reaches the target value 0.5 seconds later. It is therefore sufficient to wait slightly longer than two seconds, before the target voltage is stable.

When scanning those 27 measuring events, it has to be ensured that the DCF77 signal is steady:

To the right is the flowchart of the software for the scan phase. The flag bMax is set every 9.121 ms from the maximum detection and average calculating interrupt service routine of the ADC. First the set flag has to be cleared. It has then to be checked whether the maximum is above the set limit. If that is the case, the OC0B-PWM has to switched on to increase the negative voltage on the gain-regulating FET, and with that to decrease the gain of the OpAmp.

If not, the maximum is compared with the selected minimum level of the signal. If that is not reached, it has to be waited with the OC0B output off, until the gate voltage has decreased and the gain of the OpAmp has accordingly increased.

If both tests have been absolved correct, it is checked whether the bScan flag is set or cleared. If cleared, a scan is active. If not, see other flowcharts for what is going on then.

In case of an active scan, the wait flag bWait is checked if a wait phase is going on. If that is the case, the counter rLTCnt is decresed. If that is zero, the wait flag is cleared.

If the wait phase is over, the phase that adds together 256 max and average values starts. As the average is calculated for 256 measurments, the MSB of the sum delivers the average directly.

If the counter rLTCnt reaches zero after being decreased, the difference between the MSBs of the max and average sums are subtracted and compared with the current maximum difference value in rDiffMa. If the difference is larger or equal than the current maximum, the new maximum and the current OC0A value are stored.

Then eight is subtracted from the OCR0A value. If that value is larger or equal the minimum (adjustable by a software constant), the next scan is started by again setting the wait flag.

If the OCR0A value is smaller the minimum, the scan is complete. The maximum OC0A value is written to OCR0A and the scan complete flag bScan is set. That starts the normal operation.

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10.3.6 The AFC under normal circumstances

After the scan and under normal operation, the AFC is adjusted constantly with the following algorithm:
  1. The long-term difference between the maximum and the average is measured and stored.
  2. The OCR0A value is decreased by one, and following a 2-second wait period the difference is again measured.
  3. Then, the OCR0A value is increased by two and again after a 2 second wait the difference is again measured.
The maximum of the three values is used to adjust the OCR0A value.

This algorithm follows the normal DCF77 detection algorithm and works constantly.

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10.3.7 Analyzing the DCF77 signal

$$To be done$$

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10.3.8 Converting the DCF77 bits to date and time

$$To be done$$

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10.3.9 Transmitting the status and results

Transmitting uses TC1 as baud rate timer. As TC1 has a prescaler that allows all divider rates from 1 to 16,384, nearly any baud rate can be selected. Note that baud rates above 50 kHz are increasingly inaccurate. See the two constants cBaudEff for the factual baud rate and cBaudDiff for difference in 0.01 percent resolution. E.g. async serial transmission with 9k6 kBd transmits with 9,615 Bd effectively, which is by 0.16% too high.

During the data collection phase, to-be-transmitted data is collected in a SRAM buffer area from sBuf to sBufEnd. On completion, a carriage return and a line feed charcter is added to the buffer. Finally, a Null character is added that termintes the transmission process.

If the buffer is complete,
  1. the pointer X is pointed to the beginning of the buffer,
  2. in the case of sync transmit, the phase counter in rTxCnt is set to 2,
  3. a one is written to rTxBit to enforce reading the first character,
  4. the flag bTx in the flag register rFlag is set,
  5. the counter's TCNT1 value is set to zero, and
  6. the counter's OCIE1A is set to one to enable interrupts.
The complete transmission is then running within the interrupt service routine. The routine is programmed in two versions, according to the mode settings in cTxMode.

In both modes, reversing the data (and in sync mode the clock) pin's polarity can be reversed. The constant cReverse is responsible for that.

As async and sync transmission differ slightly, the following subchapters provide more details.

10.3.9.1 Synchroneous transmitting

Serial sync flow diagram The flow diagram shows the interrupt execution on TC1's compare match interrupt service routine. Red numbers are the clock pulses needed for each instruction.

When sync serial transmission is selected, the interrupt is executed three times more than in async mode, because each bit requires three phases to be transmitted. These phases are handled in the register rTxCnt. Phases 1 and 0 only activate and deactivate the CLOCK output pin PB2 and set the next phase count value. Phase 2 (lower side of the flow diagram) starts with the bit counter decreased. If the bit counter reaches zero, the next character is read from the buffer. If that character is zero, the flag bit bTx is cleared, the data output PB4 is switched low, the interrrupts of TC1 are disabled, and the SREG is restored.

All cases of the flow need less than 33 clock cycles to execute. Therefore the fast ADC interrupts are not affected by the transmission interrupts. That would only be the case if the baud rate is higher than 56.34 kBd: in that case TC1 would block the ATtiny25 and no other interrupts would be possible. The source code limits the maximum permissible baud rate in sync mode at 50 kBd.

If cTxContent selects transmitting the short formatted time only, "Thh:mm:ss+CR/LF" has to be transmitted, which are 11 characters per minute or second. At a baud rate of 10 kBd that lasts 8.8 ms.

If the long format is selected, "Thh:mm:ssDdd.MM.yyWD+CR/LF" 22 characters have to be transmitted, which lasts 17.6 ms.

Serial sync transmit of AA with 10 kBd This shows the transmission of hexadecimal AA (=1010.1010) with 10 kBd in sync mode.

10.3.9.2 Asynchroneous transmitting

Serial async transmission flow The flow diagram shows the interrupt execution on TC1's compare match interrupt service routine when async serial transmission is selected. Red numbers are again the clock pulses needed for each instruction.

When async serial transmission is selected, each interrupt stands for one bit. The start bit and the two stop bits add three bits to be transmitted. Each of these bits has the same duration, phases like needed in sync are not applicable here.

The interrupt service routine starts with decreasing the number of bits to be transmitted in rTxBit. If that yields zero, the next character is read from the SRAM buffer. If that is a zero byte, transmission ends by clearing the bTx flag and the output pin and suspending the compare match A interrupts of TC1. If not zero, the start bit is transmitted.

If bits are still to be send, a comparision of rTxBit with 3 yields a carry if the stop bits are to be send. This is done by clearing the output pin.

If bits of the character are to be send, the character in rTx is right-shifted into the carry flag and the output pin follows the carry.

All cases of the flow need less than 21 clock cycles to execute. Per character to be transmitted 29 clock cycles are necessary, which includes the clock cycles needed for start- and stop-bits. The maximum transmission speed is 137.93 kBd. The source code limits the maximum permissible baud rate in async mode at 130 kBd.

The minimum baudrate is below 45 Bd, small enough even for a radioamateur in Low-Speed Short Wave mode. So go ahead and start a local DCF77 date/time broadcast service over RTTY in the 40m- or 80m-Band.

If cTxContent selects transmitting the short formatted time only, "Thh:mm:ss+CR/LF" has to be transmitted, which are 11 characters per minute or second. At a baud rate of 9.6 kBd that lasts 12.6 ms.

If the long format is selected, "Thh:mm:ssDdd.MM.yyWD+CR/LF" 22 characters have to be transmitted, which lasts 25.21 ms.

This shows to the left the transmission of hexadecimal AA (=1010.1010) with 9.6 kBd in async mode, to the right the signal is reverted (as it can supplied into a MAX232).

Async serial transmit of AA with 9.6 kBd Async serial transmit of AA with 9.6 kBd, reverted


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