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DCF77 controller with ATtiny45

5 DCF77 controller with ATtiny45

To ensure that the DCF77 clock owner does not have to adjust its frequency and gain steadily and with a trim resistor, and to ensure that the DCF77 information does not have to be decoded by counting and assembling single bits, a small controller has been developed that does all that: taking care for the receiver and decode the DCF77 bits.

The results of that control are
  1. two PWM signals:
    1. a gain control signal, ranging from 0 to 255, where larger numbers decrease the gain of the receiver, so that enough, but not too large DC from the AM rectifier results,
    2. a frequency control signal, ranging from 0 to 255, which increases the varactor diode's capacity with increasing values and frequently tries out, if an increased or decreased voltage increases the drop difference of the rectified DCF77 signal, by that keeping the input frequency of the ferrite antenna always on the center of DCF77's transmit frequency,
  2. the checking that amplitude drop and pause times of the DCF77 signal are within the correct expected times of 100 or 200 ms (for a zero or one bit received), of 800 resp. 900 (for an inactive pause with high amplitude following reception of a one or zero bit) or of a high amplitude for either 1800 or 1900 milliseconds (minute change following reception of the 59th or last one or zero bit), times plus and minus a selectable tolerance percentage,
  3. to collect DCF77 bits, if the 100 or 200 ms long amplitude drops occur, and to store those 59 bits per minute in a correct row in the SRAM,
  4. on a minute change correctly received: to check all parity bits of DCF77 (minutes, hours, date) for correctness,
  5. to convert the received bits for minutes, hours, weekday, day, month and year from BCD to binary format, and to
  6. send all those information, including error messages and status information, over a one-way two-wire interface to another controller, that can receive and display all that on an LCD.

5.1 Why assembler? Why an ATtiny45 and nothing else?

Lots of things to do for The additional controller to display those signals on an LCD was necessary to have all the pro's of the ATtiny45 PWM features and to allow the use of other controllers for the display or if you need any further DCF77-date-and-time-dependent switching only. If you need only two or three channels to be switched on and off only during weekdays you can use an ATtiny13 instead: connect serial clock with INT0, serial data with any other pin and the two or three output pins with your switches. The DCF77 controller says which weekday currently is and which time and date. Even if DCF77 is off: the status messages allow to detect such failures and to switch to a software-driven clock scheme instead.

5.2 The schematic of the ATtiny45 controller for DCF77

DCF77 controller schematic This is all you need. It works with an ATtiny45 or ATtiny85.

The two PWM outputs OC1A and OC1B generate the two voltages for AGC and AFC and use the high-speed-PWM features of the ATtiny45/85. The High-Speed PWM oscillator of 64 MHz is switched by software to low speed (32 MHz is sufficient), then divided by 8 in the prescaler, to yield a PWM frequency of 31.25 kHz. Both outputs are connected to a two-stage RC network of 10kΩ and 1µF. This ensures that digital humming is small enough and that the analog voltages produced react fast enough to any changes of the PWM value.

The rectified and RC filtered (0.01 ms) AM DC signal from the DCF77 receiver is fed to the AD converter channel ADC3. Conversion is clocked by TC0's timer overflow, that occurs every 16.4 ms. The amplitude drop of 100 ms length for a transmitted zero results in six, for a one in approximately twelve measurements. A zero and a one, followed by a minute change pause of approximately 1,800 ms, happen within three seconds or over 183 measurements. The storage of such measurement results, in order to calculate averages and to measure pulse durations, requires 183 SRAM bytes. That is why the ATtiny25 does not fit.

The whole time and date detection of the DCF77 signal as well as the AGC and AFC control is based on this collection. No further RC filters are necessary (like this wou÷ld be the case to detect the minute change in the DCF77 signal, see the chapter on how-it-works here).

Serial output of the results is done with the pins PB0 (data master, SDM) and PB2 (clock master, SCM). As communication in backwards direction is unnecessary, both outputs are always master and active. The two LEDs can be used to view active signal traffic.

The ISP interface can be used to program the chip within. It is not necessary if pre-programmed ATtiny45/85 are used.

5.3 Functioning

5.3.1 Start-up phase

When the controller starts, it absolves a start-up phase. This adjusts the AGC and the AFC to start-up values. Both start with decimal 255 in their PWM channels or +5V. On every complete batch of 155 measurements the AGC value is decreased by eight (maximum 32 batches or 81 seconds). The decrease stops if either
  1. a minimum of 0.5 V has been reached, or
  2. a maximum of 2.5 V has been exceeded, or
  3. zero has been reached.
In any case the first approach of AGC adjustment is over then, further adjustment is taken over by each completed batch by
  1. increasing the PWM value, if the maximum is larger than 2.5 V, or
  2. decreasing the PWM value, if the maximum is smaller than 2.0 V.
In the second phase the AGC value is adjusted. After each batch the AGC PWM is decreased and the difference between maximum and minimum is stored in SRAM. This phase is stopped when the AFC PWM value reaches zero (which takes another 81 seconds).

Software then searches for the first maximum value in the stored values, starting from the difference at the PWM value of 255. This is done because, in case of a larger ferrite coil, a second maximum can occur that relates to one of the two coils, which can be even stronger than the combined one, but signal strength at that decreases very fast if the direction of the ferrite changes slightly. If the first maximum is identified, the AFC PWM is written to that value.

Further frequency adjustment is then done on each batch completion: the AFC PWM value is increased, and then decreased, and the difference of the maximum and minimum decides, whether the last change is repeated (if the difference is larger) or if the direction changes (if the difference is smaller). If the maximum has not been found during the AFC scan period, the frequency scan is repeated over and over again.

5.3.2 Detection of zero/one bits and minute change

During the AGC and AFC scan periods normal checking of incoming single values is omitted. Only if both the bGScan and bFScan flags are set, the single values are checked whether a level change has happened. To do that, the last three measurements, as stored in three registers and updated whenever a new measurement is completed, are compared with the average value. The average value is updated whenever a complete batch has been measured, it is the maximum value minus the minimum value.

If the last values were inactive (higher than average) it is waited for three succeeding values below average. If those are detected If the previously recognized stage was a signal coming in (three values were below average) the last three values are checked for a signal end. If all three are above average the detection of high-to-low signals is switched on. The signal duration of the low-signal is checked for the minimum length of a zero and its maximum as well as for a one with its minimum and maximum. If a correct zero or one has been identified, the respective bit is shifted into the bit storage and counted. If not, respective error messages are send via the serial interface.

5.3.3 Generation and properties of the PWM signals

The two outputs OC1A and OC1B generate PWM signals for adjusting gain and frequency. 8-bit timer TC1 is in asynch mode: the PWM clock is at 64 MHz, slowed down by two and is divided by 8. The PWM width is 256 stages, so the resulting PWM frequency is 64 MHz / 2 / 8 / 256 = 15.625 kHz or a PWM period of 64 µs.

To filter the harmonics, a double RC filter with 10kΩ and 1µF follow. The filter was simulated with the Libre-Office spreadsheet here. On start-up, when both capacitors are unloaded and the PWM is set to 255, the following voltage increase happens.

PWM RC filter on start-up and massive changes The increasing curve shows that the RC filter has nearly complete the end point after 0.1 seconds and completely after 0.2 s. That is fast enough to not having to wait on start-up for the stabilized voltage. The second capacitor follows slightly behind, but is also fast enough.

The change speed from full load down to zero (not exactly zero, as the PWM has a minimum of 1, which corresponds to a minimum of 19.5 mV), is similar. The end value is reached within 0.2 s.

PWM RC filter at small level changes To demonstrate the speed of change for a small difference in PWM values, this shows the voltages on both capacitors if the PWM is switched from 255 down to 254 (normal switching is by one unit, 19.5 mV). The first capacitor shows voltage drops (humming) of 3 to 4 mV by the single low phase among 255 high phases, the second capacitor is completely free of this humming.

The voltage on C2 is a bit delayed, but by less than 5 ms. That is fast enough for the AFC and AGC adjustment, the next ADC measurement after 16.384 ms will already reflect the new voltage setting.

Do not try this with a different type of ATtiny or a different controller, it does not work due to lower PWM frequencies.

5.3.4 Measuring and evaluation of the AM DC signals

Analysis of the amplitudes To ensure that measuring the amplitude voltage in constant time slices the AD conversion is started by the overflow of timer TC0 using the ADATE bit of the ADC. The TC0 prescaler is set to 64, so that the conversion starts all 256 * 64 * 1,000 / 1,000,000 = 16.384 ms. The conversion, with an ADC clock prescaler of 128, needs 1.664 ms (see section Timing in the source code).

Reading of the ADC values is performed within the ADC's interrupt service routine:
  1. only the upper 8 bits of the result are read (ADLAR is activated),
  2. the value read is written to the registers rLast, so that the last three measurements are available in the registers rLast1 to rLast3, because the amplitude drop detection is based on those three values (outside the ISR),
  3. the value is written to an SRAM buffer sBuffer, that is adjusted to a length of 155 measurements, corresponding to the last 155 * 16.384 ms = 2.54 seconds.
If the buffer is full, the flag bBufFull in the flag register rFlag is set. Outside the interrupt service routine this bit is recognized and the complete buffer is searched for the maximum and minimum values. The difference between the two extremes is then
  1. evaluated if the minimum difference in cAmVoltDelta has been reached. If this is not the case, error message E0 (DCF77 signal time-out) is issued over the serial interface, further bit evaluation is blocked by setting the bMin flag in the flag register and a frequency scan is re-started by clearing the bFScan flag,
  2. divided by two and added to the minimum value. This value is used as compare value to decide whether the signal strength is above or below the average value.
The maximum, average and difference values are applied until the next buffer is filled (after 2.54 seconds). From the measured difference value the AGC adjustment is derived on every buffer-full event:
  1. The PWM value is either increased or decreased in the next period, depending from the result of the last increase or decrease.
  2. If the last change was an increase:
  3. If the last change was a decrease the opposite is performed.
That means, that in case that the difference is equal, the direction is changing each time the buffer is full, and that the PWM value constantly goes up and down by one unit.

The AGC PWM is adjusted as follows:
  1. if the maximum value is smaller than 2.0 V, the gain is increased by decreasing the PWM compare value by 1,
  2. if the maximum value is larger than 2.5 V, the gain is decreased by increasing the PWM compare value by 1,
  3. if the maximum is in between 2.0 and 2.5 V, the PWM value is not changed.

If neither bGScan nor bFScan are cleared, the edge detection is active. Edge detection works as follows:
  1. The flag bHi in the flag register stores if the last edge was a low-to-high transition, the register rTransH:rTransL holds the SRAM buffer position when the last transition happened.
  2. If bHi is set, an amplitude drop is to be detected. It is checked whether the last three values in rLast1, rLast2 and rLast3 are all below the average value. If that is not the case the detection routine ends and waits for the next value. If it is the case,
  3. If bHi is clear, the next rising edge is to be detected. This is the case if all rLast registers are above average. If this is the case,

5.3.5 Serial transmission

The serial transmit routine is called whenever the ADC reports a single measurement result (any 16.384 ms) and after all actions to be taken are completed. The messages to be send are written into a ring buffer in SRAM, with two bytes for each message. The buffer input and output addresses are held in two register pairs. On calling the send routine it is checked whether input and output addresses are equal. If that is the case, nothing is send.

If there are messages to be send,
  1. the message is copied (2 bytes),
  2. it is send bit-by-bit (starting with bit 15 down to 0) over the serial pins by and for all 16 bits,
  3. increasing the message output address by two.
The receiver has to be able to receive each bit within 50 µs (at 10 kBd) resp. 25 µs (at 20 kBd). A PCINT in the receiver, with shifting the bits and counting, takes 27 clock cycles, so the receiver has to work with at least a clock rate of 540 kHz at 10 kBd or 1.08 MHz at 20 kBd. So the default is set to 10 kBd to be compatible with a 1 MHz clock rate of the receiver.

Timing of the controller's tasks If necessary, any 16.384 ms a data set transmit requires 800 or 1,600 µs time. For flag handling and all other operations nearly the complete time between this and the next ADC event is available (16.3 milliseconds), because the AD conversion does not need any action. Transmit baud-rates of 10 or 20 kBd are compatible, the lowest possible baud-rate would be roughly 8 ms for 16 Bits = 2 kBd.

Lots of different information have to be send to the receiver. To ease processing of those in the receiver, the 16 bits were divided into the MSB, consisting of an ASCII character, and a second LSB that holds an additional parameter. All message codes are listed in the table, in "" enclosed characters are ASCII, in () enclosed values are binary numbers.

ParameterHigh ByteLow ByteDuration (ms)
Frequency scan completed"C"0=not ok, 1=ok
Signal strength"S"(AGC value)
Frequency"F"(AFC value)
Received DCF77 time98.3
Bit monitoring16.4
Zero received"0"0
One received"1"1
DCF77 error messages16.4
Short signal"E""1"
Between zero/one"E""2"
Between one/pause"E""3"
Between pause/minute"E""4"
Longer than minute"E""5"
<>59 bits"E""6"
Number of bits"B"(Number of received bits)
Parity minutes odd"E""7"
Minute ones > 9"E""8"
Minutes > 59"E""9"
Parity hours odd"E""A"
Hours ones > 9"E""B"
Hours > 23"E""C"
Parity date odd"E""D"
Weekday = 0"E""E"
Day = 0"E""F"
Day ones > 9"E""G"
Day > 31"E""H"
Month = 0"E""I"
Month ones > 9"E""J"
Month > 12"E""K"
Year ones > 9"E""L"
Year > 99"E""M"
Debugging messages32.8
Buffer filled"a"(Average value)
Delta max - min"d"(Difference)

All transmitted time and data of a successfully evaluated DCF77 signal set require approximately 100 ms. This can be used to adjust the seconds counter of the receiver clock to synchronize the start of the next minute.

The debugging messages are only send if the respective debugging switches are set to Yes.

The signals that the transmitter produces look like shown here (left: 10 kBd, right: 20 kBd). Send here was 0xAAAA (ones and zeroes). The data signal on PB0 (SDM) is red, the clock signal on PB2 (SCM) is green.

Serial signal 10 kB Serial signal 20 kB

5.4 Software


5.5 Operation experiences


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