Path: Home => AVR overview => Applications => DCF77 receivers => Controller tn25   Diese Seite in Deutsch: Flag DE
DCF77 receiver logo Applications of
AVR single chip controllers AT90S, ATtiny, ATmega and ATxmega
DCF77 AM controller with an ATtiny25
Logo
This project is experimental. I don't know if it really works as planned here.

10 DCF77 AM controller with an ATtiny25

This controller with an ATtiny25 does the following:
  1. it measures the amplitude of the receiver's HF or IF and rectifies it,
  2. if the amplitude is above or below the admissible voltage, it
  3. it performs an AFC scan at the beginning to find the frequency of DCF77 and regulates this frequency during operation,
  4. it collects DCF77 bits, checks those for correctness and converts those to time and date strings, and
  5. outputs either raw amplitude data or time-and-date strings on one or two output pins.
The output of the ATtiny25 on the two pins 3 and 7 can be configured as follows:
  1. no signal, both pins remain low, or
  2. original DCF77 signal on pin 3, inverted DCF77 signal on pin 7, no decoding or change in the signal, or
  3. decoded time and date transmitted over two synchronous output pins, or
  4. decoded time and date transmitted over an asynchronous output pin, if the respective Clear-To-Send pin is on.
The constant cTxContent determines which content is transmitted in modes 2 or 3:
  1. nothing, or
  2. decoded time transmitted as serial ASCII each minute, in the format "T14:59" as derived from the decoded DCF77 signal, or
  3. decoded time and date as serial ASCII each minute, in the format "T14:59D12/20/20WSu", or
  4. the latter, but additional receiver status and debugging info added as lines, which do not start with a T.
Conversion of the ME(S)T time to UTC can be configured within the software by setting cUtc to one.

The controller here can be used for any direct or suphet receiver. The following controllers can be attached to receive and display the results:
  1. convert the controller's async signal to a RS232 signal and receive and display it with a PC or laptop and a terminal program,
  2. add a sync receiver with an ATtiny24 and an LCD here, or
  3. add an async receiver with an ATmega48 and an LCD here, or
  4. add an async receiver with an ATmega324 and a muxed 4-digit 7-segment LED here.
A stand-alone version that uses the ATmega324 instead of the ATtiny25 controller, which is equipped with an LCD and a two-way RS232 interface, is presented here.

10.0 Index

  1. Hardware
  2. Software download
  3. Software overview
  4. The AD conversion of the input signal
  5. The AGC control via the OCR0B-PWM
  6. The AFC scan at start-up
  7. The AFC under normal circumstances
  8. Analyzing the DCF77 signal
  9. Converting the DCF77 bits to date and time
  10. Transmitting the status and results
All drawings are available as Libre-Office-Draw file here.

10.2 Hardware of the ATtiny25 controller

The ATtiny25 controller Control and regulation as well as analyzing the DCF77 signals is the task of an 8-pin ATtiny25. You can also use an ATtiny45 or 85, if you want to waste unused flash and EEPROM memory space.

The following functions are implemented:
  1. measuring the amplitude of the DCF77 signal on pin ADC3 (pin 2),
  2. generating the AFC control voltage on the OC0B output pin (pin 6), and
  3. generating and outputting the desired results via pin 3 (either the original DCF77 amplitude state, the data for sync serial transmission or the TXD signal for async transmission) and pin 7 (either the inverted DCF signal, the Clock signal for serial sync or the CTS input for async serial signals).
These hardware functions are described nearer in the following chapters.

Top of page Index Hardware Software

10.2.1 Measuring the DCF77 signal

The ATtiny25 measures continuously the maximum amplitude value of the OpAmp's output on his ADC3 input. As the signal swings around the medium voltage of 2.5 V, these values are rectified mathematically, so that even unsymmetrical signals can be measured correct.

The software then determines two values from 256 of such measurements:
  1. the maximum amplitude value (above or below the average), and
  2. the average of the signal.
The second value should be around +2.5V (8-bit-ADC value = 128) and serves only for the mathematical rectification of the signal.

The first value controls the AGC pin OC0B. In analog mode the AGC voltage is increased or decreased if the long-term maximum is below or over +2.5+1.5=4.0 V. If negative voltage generation is selected, the voltage generator is switched on if the long-term maximum is smaller than +2.5+0.5=3.0 V. If 4.0 V are reached, the AGC voltage generator is switched off.

The further treatment of the measured maximum values is described in the software section below.

Top of page Index Hardware Software

10.2.2 Generating and filtering the AFC voltage

OC0A as AFC controller Die OC0A PWM fuer die automatische Frequenzkontrolle The OC0A-PWM generates a pulse-width-modulated 8-bit-rectangle, which is filtered with a three-stage RC network. The output controls the three varicaps on the LC circuit.

The three stages are necessary to remove PWM noise from that signal. In the first stage there are still 420 mV ripple (see calculation sheet controller_OC0A in the Libre-Office Calc file here). In the second stage this goes down to 19 mV, in the final stage to 3.6 mV. This ripple varies the LC input stage by roughly 7.2 Hz, small enough for operating the LC stage and below the 256-stage resolution of the PWM (40 Hz per digit).

Response of the AFC filter network The very good filter properties of the RC have an adverse effect: it delays adoption to changed PWM values. The delay when changing the PWM value by 8 lasts roughly 2 seconds, as shown in this diagram. Changes by 8 occur at start-up when the AFC is scanned to find the first approach to the optimum value. That means that the software has to wait for two seconds until the changed voltage has settled.

Scanning is performed at the beginning. The OCR0A value is set to 255 and is reduced by 8 in 28 stages. After the delay the maximum and its average is measured for 256 times (=65,536 measurements, 2.3 seconds long). The difference between the maximum and its average helps to identify whether the input signal at this frequency is a steady-amplitude transmitter or is DCF77. This because the low-amplitude phases of DCF77 reduce the average, and in 2.3 seconds at least one amplitude reduction takes place. This is simulated in the following diagram over 80 seconds long. Maximum and itrs average The OCR0A value at the maximum difference between maximum and its average is finally selected as start value for the AFC and written to the OCR0A portregister.

As each scan value is settling over 2.3 seconds and then measured over 2.3 seconds, the whole scan phase lasts 129 seconds or two minutes long.

The further adjustment of the AFC is performed during normal operation. Here, the OCR0A values are varied by +/-1. More about the scan phase and AFC adjustment during operation can be found in the software section.

Top of page Index Hardware Software

10.2.3 Generation and filtering of the AGC voltage

AGC voltage generator AGC voltage loading/unloading The generation of the negative control voltage for the gate of the FET (AGC) is done with a coil, two capacitors of 470 nF and two Germanium-Diodes. If OC0B produces a rectangle, this generator delivers -4.6 V, if permanently on. This is enough for all types of FET (A to C types). Driving the OCR0B-PWM output with other OC0B compare values than 0x7F has nearly no effect, the control voltage has to be regulated by switching the output pin OC0B off and on, the long time constant of 10 MΩ * 470 µF is long enough to not change control voltages too fast, e. g. when DCF77 is reducing its amplitude to transmit a zero (100 ms) or a one (200 ms), and to smooth the signal during pump phases (when full, the AC on that 470 µF capacitor is at less than 1 mV).

If the generator is off, the capacitor unloads via the resistor. This increases the negative gate voltage to more positive values, RDSon of the FET gets smaller, the divider between the OpAmp stages lets less amplitude through to the second OpAmp and so reduces the overall gain.

At start-up, the capacitor is unloaded and RDSon has its lowest value. So, on start-up no input signal in the second stage is present. Only after the OC0B-generator has produced enough load, the second stage starts amplifying. Loading ends when the maximum allowed amplitude has been reached.

During normal operation, if the long-term amplitude maximum falls below a minimum value, the generator is again switched on. As the 2.3-second average always includes one or two amplitude drops, the generator does not react on short-term drops.

On more details on the algorithm that controls the AGC voltage see the software section below.

Top of page Index Hardware Software

10.2.4 Output of results

The two pins PB2 and PB4 produce the output signal, depending from the selections in the source code:
  1. If the constant cTxMode is zero, both output pins are permanently low.
  2. If the simplest method 1 is selected, pin 3 (Data) follows the DCF77's signal strength: normally high, when a zero or one is transmitted it goes low. Note that for recognizing a low at least three maximum values below the long-term maximum average is necessary, so that a delay of 30 ms occurs. For those who need an inverted signal: just use the output pin 7 (Clock/TXD) or set constant cRevert to one.
  3. If serial synchronous output is selected with bTxMode = 2, data and messages are send over the two pins. The bits of the character stream are placed on the DATA pin 3, starting with bit 0, the CLOCK pin 7 is activated for one third of the time per bit (baud rate) and after another third the next bit is placed on the DATA pin. All content is send as ASCII characters. The baud rate can be adjusted by the constant cBaud (in Baud or bit per second).

    Synchronous transmission over the Two-Wire-Interface

    The scheme shows transmission of a 0xAA byte with 10  kBd. The three phases allows the receiver to prepare and perform its actions. Each eight bits form one character, all bits are send without additional pauses in between. The end of a transmitted line is finalized with a carriage return and a line feed character.
  4. In mode 3 all results and messages are send in asynchronous mode, with a start bit and two stop bits (1N8), over the DATA/TXD pin:

    Asynchronous transmission

    This shows such a transmission over a RS232 line, with a baud rate of 9k6. The +/- 12V level over the RS232 line can be seen. Such a level converter looks like this:

    Async RS232 level converter Only the CTS signal of the RS232 is used: it has to be activated to allow transmission. Baud rates are adjusted with the cBaud constant, cRevert = 1 inverts both signals. Lines are finalized with CR and LF again.
The selection of what shall be transmitted can be adjusted in cTxContent:
  1. Zero transmits nothing.
  2. One transmits the time in the format "Thh:mm:ss", preceeded by a T. It follows a M for Mid-European-Time, a S for Mid-European-Summer-Time or a U for UTC. A CR+LF follows.
  3. Two transmits the time, preceeded by T, then M/S/U for the time format, then a D for the following date. If cEN in the ATtiny25 is one, the date is send as "MM/DD/YY", if zero as "DD.MM.YY". Then a W and the two characters of the weekday follow, finalized by CR+LF.
  4. Three additionally sends relevant messages on the status of the controller such as the adjusted AFC-PWM value as "F = 123" and the state of the AGC generator as "G = On/Off" and so-called E numbers with DCF77 time/date conversion errors, as well as time and date in the long format like above.
See the software section for more on that.

Top of page Index Hardware Software

10.3 The software

10.3.1 Software download

The software is still under construction. $$To be done$$

10.3.2 Software overview

The software has to do the following:
  1. The DCF signal that comes in from the ADC3 input pin has to be converted to a digital value, has to be rectified (as positive distance from the averaged mean value) and from that This is all done within the interrupt service routine. To speed things up, only the 8 most significant bits are read from the ADC and averaging sums up those raw values in a 16-bit register pair. After 256 measurements (roughly 7.3 ms) the MSB of the sum is copied to the register rAvg. This value is only used to determine the rectifier's mid value, to be subtracted from. If subtraction of the average from the ADC raw result sets the carry flag, the value is complemented (subtracted from zero). This value is then compared with the previous maximum in rMaxM and, if larger or equal, replaces this maximum. After 256 measurements the value is copied to rMax and the bAdc flag is set. Further processing is outside the interrupt service routine.
  2. Outside the ISR it is checked whether the AGC generator is currently on (bGain = 0). If this is the case and if the rMax value is equal or above the selected value in cMaxLevel (2 Vrectified = 4 Vpp) the AGC generator is switched off, the flag bGain is set and the long-term averaging of the maximum is restarted.
  3. If not currently charging the AGC, the long-term maximum is calculated by summing up 256 maximum values. The MSB of this sum is written to rLTMax. If this value is smaller than the minimum level in cMinLevel (0.5 V) the AGC generator is switched on again and the flag bGain is cleared.
  4. If not, the DCF77 signal recognition is performed as follows:
    1. If the previous amplitude was high (flag bHigh = 1) and if the short-term maximum is smaller than the long-term average maximum, a cycle counter is decreased (from three down to to zero). If that is the case, the amplitude has changed to low. In that case bHigh is cleared and the cycle counter is checked whether the high phase counter is within the bounds of a minute change. If so, a minute change is performed.
    2. If the previous amplitude was low (flag bHigh = 0), the same mechanism takes place. If this phase ends, with the three-counter reaching zero, it is checked whether the previos low-phase was in the range of a zero or a one.
  5. If output options are enabled, the respective outputs have to be written to the output buffer and buffer transmission is started. These parts are only assembled if so enabled.
To adjust the AFC voltage,
  1. a scan at the beginning finds the raw area, where DCF77 transmits, and
  2. during the decoding running, the PWR is running with one digit lower and one digit higher values, which allows a fine identification.
Long-term averages of maxima The scan works as follows. It starts with the highest possible voltage that TC0 can produce (OCR0A at 255 respective +5V, lowest capacity of the varactors, highest frequency of the LC)- After waiting for 2.3 seconds to accommodate the RC network to the new value, the 256 maxima are measured, for which the maximum and the average are calculated. If the difference between the maximum and its average is higher, this value is saved. Then the value of the PWM is decreased and the same procedure is repeated. If the PWM value reaches its minimum (by default 39), the scan ends and the OCR0A value at the detected maximum is written to OCR0A.

See below for a flow diagram of this scan.

When running normal, the PWM value is varied with -/+ 1 digit and the same difference is used to re-adjust the AFC to one of the values -1, 0 or +1.
Top of page Index Hardware Software

10.3.3 The AD conversion of the input signal

The AD converter runs in free autostart mode, which means: it restarts the AD whenever the previous result has been read. As the ADC has to detect the maximum of the 77.5 kHz DCF77 wave, it runs nearly as fast as possible (2 MHz controller clock, AD prescaler = 4, AD frequency roughly 35 kHz). So it measures approximately one value per two sine waves on the input. An analysis shows that this is sufficient and does not produce too much erronous values. Result fetch, maximum detection and average calculation is performed within the ISR of the ADC.

The timing is shown in the calculation sheet DCF77clocking of the Libre-Office file here, with the parameters in the sheet controller_ADC. The sheet controller_maxdetection simulates the maximum detection over 256 measurements. As the ADC is restarted only after the previous result has been read, the effective number of conversion cycles is 14.25. Sampling 256 measurements lasts roughly 7,3 ms.

To avoid lengthy division routines, the average calculation over 256 measurements is held as simple as possible. Because only 8-bit values are relevant here, the ADLAR bit of the ADC is set and only the high byte of the result is read.

The detection of the maximum and the calculation of the average are done within the interrupt service routine. This needs between 27 and 32 clock cycles for that. If the controller would be at its default 1 MHz clock and the AD prescaler would be two, one measurement would last 28 controller clock cycles. That means that there is no time left to do something else, e. g. for transmitting or calculating long-term averages, but to collect AD values and restart the ADC. Therefore the default clock of the ATtiny25 of 1 MHz is increased to 2 MHz, for which the clock prescaler CLKPR is set to four at the beginning. At 2 MHz clock the controller provides enough spare time for the 27 to 32 clock cycles of the ISR as well as for other purposes such as transmitting.

Top of page Index Hardware Software

10.3.4 OC0A and OC0B adjustment: The AFC scan at start-up

Flow diagram of the scan phase This flow diagram shows the scan phase, that starts after beginning and that is performed outside the ISR. The ISR of TC0 initiates this every 10 ms by setting its flag bit, if its down-counter reaches zero.

At start-up the 470 µF capacitor is not loaded and starts loading. In this phase it is only checked if the maximum is below the threshold level. If this is the case, nothing else happens. If the threshold has been reached, the bGain bit is set, the generator is switched off, the averages are restarted and normal processing can begin.

By summing up 256 short-term measurements of the maximum an average of the maximum over 2.3 seconds is calculated. If those 256 measurements are available, it is checked whether the maximum are below the selected min level. If that is the case, the generator is restarted again and bGain is cleared.

If the 256 values have enough amplitude, the MSB of the maximum and the MSB of the sum is stored in the long-term registers for further use.

At start-up the raw adjustment of the frequency has to be performed. During this time, the bScan bit is clear. Scanning starts with 255 in the OCR0A port.

This phase is necessary because there could be other transmitters within the LC reception band:
  1. At first: the tenth harmonic of the TC0-PWM, that produces the AFC voltage and that generates the AGC voltage from time-to-time is at 78.12 kHz and not very far from DCF77. So better not waste space and place the antenna circuit as far away from the ATtiny25 and the PWM components as possible. Anyway, this does not produce an amplitude-modulated signal but a steady noise.
  2. Here at my location south of Frankfurt a strong signal on 80 kHz is seen, for which I do not know where it is coming from.
  3. My energy saving lamp transmits constantly near 70 kHz.
It is insufficient to measure only the maximum of the received waves, because you would be stuck to these constant-carrier-signals instead of DCF77. So it is the second-pulses that are the relevant detection criteria for DCF signals. Only the signals where the maximum is by 10 or 20% larger than the average maximum promise to the DCF77 carrier.

As long as the scan is active a bWait bit = 0 lets the scan continue for another 2.3 seconds. Only if this bit has become one, the value is read and compared with the previous ones. Each of the 28 measurements in the scan phase is evaluated for this difference, the maximum difference and its associated OCR0A value are stored.

In each scan step the OCR0A value is decreased by 8 until it becomes smaller than 39 (AFC = 0.76 V). If that is reached, the scan ends and the optimal OCR0A value is written to OCR0A.

Top of page Index Hardware Software

10.3.5 The AFC in normal operation

After absolving the raw scan, the following algorithm adjusts the AFC voltage.
  1. The long-term difference between the long-term maximum minus the average maximum is calculated and stored in SRAM (measurement 1).
  2. The current OCR0A value is decreased by one and, after a wait period, the long-term difference is measured and registered (measurement 2).
  3. Then the OCR0A value is increased by two and the same procedure is performed (measurement 3).
The maximum of the three stored values is selected as next approach.

Top of page Index Hardware Software

10.4 Analysis of the DCF77 signals

Flow diagram of the DCF analysis This is the flow diagram of the DCF77 signal analysis. Displayed here is solely the recognition of zeros, ones and the minute changes.

It starts with halving the long-term maximum, this value is used to determine zeros and ones and high-amplitude phases. The duration counter rDcfCnt is increased by one.

Further processing depends from whether we are in a high phase of the amplitude (bHi = 1) or not. If in a low amplitude phase (left part of the diagram), it is checked whether the short-term maximum is still lower than halve the long-term maximum. If that is the case, the counter rCnt is restarted at three.

If not, the counter rCnt is decreased. If that reaches zero (after three consecutive highs), the direction bit bHi is set and the duration of the low phase is checked if it is within a zero or one range. If it is not in these two ranges (too short, between a zero and a one, longer than a one), an error is generated and processed (with output, if so configured).

Correct zeros and ones are written to the carry flag C and are shifted into the eight DCF bit storages in the SRAM (sDcfBitsN). The number of received bits is increased, if 59 is exceeded another error results.

During a high phase (right side of the diagram) the same recognition of a level change takes place. If so, the duration is compared with the range of a minute change (1800 ms - tolerance to 1900 ms plus tolerance plus one). If the duration was shorter than a minute change, it is checked whether the signal was between 800 ms - tolerance and 900 ms plus tolerance plus one. These signals appear between single bits and are ok (no error message triggered).

If a minute change has occurred, it is checked whether exactly 59 bits had been registered. Then it is checked whether the parity bits for hours, minutes and dates are correct. If that is also the case, the DCF bits are converted to time and date in ASCII (see next chapter) and, if so configured, converted to UTC (see overnext chapter). If the time and date are completed, those are send over the serial interface, if so configured.

10.4.1 Conversion of the DCF77 data bits to time/date

DCF77 bits structure This is the location of all 59 bits that result from right-shifting of all bits in SRAM.

The following remarks to that: When accessing such very long records of bytes the AVR's ability to access bytes, where Y and Z point to the base, with a distance and with LDD/STD is very helpful. To use this feature I grouped the time/date record as follows and added distance values.

Structure of the SRAM table The SRAM table is structured systematically to optimize transparency and understandably.

The column Dist gives the displacement for accessing the byte with LDD r,Y/Z+d or STD Y/Z+d, r. The formulation LD R16,Y+dStrT yields the content of the table on the position dStrT, if Y points to sDcf.

10.4.2 Checking the parity

Flow diagram Parity check This is the parity checking rountine's flow diagram. Normally, when hours and minutes parities are checked, the T flag is cleared on entry. The data byte, including its parity bit, is send into the routine and it ends with a cleared T flag, if the parity is fine. If you have to check further bytes, like in the date parity, rather call ParN which uses the previous state of the T flag instead.

Top of page Index Hardware Software

10.4.3 Conversion of the DCF77 date and time to UTC

Conversion to UTC This is rather lengthy if you want to convert time and date to UTC in a correct manner, so that the displayed date is also correct when the day already changed in ME(S)T time, but not yet in UTC time. That requires going back in the date, which is more or less complicated on the 1st of January, where anything changes, including the years.

Top of page Index Hardware Software

10.5 Serial transmission of results and status

Serial sending uses TC1 as baud rate generator and for the whole timing of the transmission process. As the 8-bit TC1 in the ATtiny25 allows prescaler values between 1 and 16,384, a rather accurate timing can be achieved. Baud rates beyond 50,000 get more rough, but who needs such high rates at all. The inaccuracy is listed in the symbol table that gavrasm as well as avr_sim produce at the end of their listing. The two constants cBaudEff (effective Baud rate) and cBaudDiff in 0,01% resolution can be see. The 9k6 async baud rate comes out with 9,615 Bd, which is by 0.16% too high. Such small differences are insignificant for a robust RS232 interface.

During operation a number of result (each minute) and status messages (each second) can come up. Those are written to a transmit buffer in SRAM, which spans from sBuf to sBufEnd. If the line is complete, carriage return and line feed characters are added as well as an ASCII-Null to end transmission.

If the buffer is ready to transmit,
  1. the pointer X points to the buffer start,
  2. in the synchronous case rTxCnt is set to two,
  3. a one is written to the bit counter rTxBit to provoke a read-next-character from buffer,
  4. the flag bTx in the flag register rFlag is set,
  5. the TC1 counter TCNT1 is overwritten with zero, and
  6. the interrupt mask register bit OCIE1A of the counter is set, by that allowing interrupts from TC1.
The complete transmission is performed within the ISR, of which two versions are in the source code and enabled by the constant cTxMode:
  1. cTxMode=2 enables the sync mode,
  2. 3 enables the async mode.
In both modes the constant b>cReverse = 1 inverts the polarity of both output pins.

Because the async- and the sync mode work different, those are described in two sub-chapters that follow.

10.5.1 Serial transmission in sync mode

Serial sync transmission flow diagram The flow diagram shows the interrupt execution of the TC1 Compare Match. The red numbers display the number of clock cycles required.

In sync mode the interrupt occurs three times more often than in async mode. The phase counter rTxCnt decides what to do next. 1 and 0 activate and deactivate the CLOCK output pin. Phase 2 places the next bit onto the DATA pin (lower part of the diagram) and decrements the number of bits to send in rTxBit. If that reaches zero, the next ASCII character is read from the buffer. If that is ASCII-Null, the transmit is terminated and the flag bTx is cleared as well as the interrupt flag of TC1. If not, the bit is placed to the DATA pin.

All different execution rows need less than 32 clock cycles. Only in a few cases ADC interrupts can be delayed, but only for short. Only in high baud rates beyond 60 kBd these cases block the complete interrupt scheme. Therefore the source code limits the sync baud rate to below 31 kBd.

If cTxContent selects the output of the short time format, the transmit routine needs, at 10 kBd, roughly 8.8 ms for that. When long format is selected, these are 18 ms long. As both occur only once in a minute, those are no relevant occasions.

Serial sync transmission of AA with 10 kBd This shows the transmission of hexadecimal 0xAA (=1010.1010) over the data and clock-Pins in sync mode.


Top of page Index Hardware Software

10.5.2 Serial transmission in async mode

Flow diagram seriell async transmission The flow diagram shows the interrupt execution in async tranmission mode.

In async mode each interrupt stands for one bit. Per 8-bit-character one start bit and two stop bits are added. Due to this the baud rate is 8/11th of the character speed.

The interrupt service routine starts with decrementing the number of bits in rTxBit. If this reaches zero, the next character is read from the SRAM buffer. If that is ASCII-zero transmission ends. If not, the start bit is send (when cRevert = 0 the start bit is high, if 1 it is low). If the number of bits to be send is smaller than three stop bits are send. On any other number of bits one further bit is shifted into carry and the TXD output is set or cleared.

All different flow pathes require at max. 27 clock cycles. The maximum baud rate, at which the transmit blocks any other activities, is 74.1 kBd. If the time for each bit is considered correct, the baud rate for a blockade is reached at 95 kBd. Therefore the baud rate in async mode is limited to 47 kBd in the source code.

The minimum baud rate is below 45 Bd, low enough to start a DCF77 time service on short wave that transmits the DCF77 time/date/weekday via a Radio-Teletype (RTTY) transmitter.

At 9k6 the long format needs 25 ms, the short format 12,6 ms.

The two simulation diagrams show the character 0xAA in async mode at 9k6, to the right the inverted signal how it can be fed into a MAX232.

Async mode of AA with 9.6 kBd Async mode of AA with 9.6 kBd, inverted


Top of page Index Hardware Software


©2020/2021 by http://www.avr-asm-tutorial.net