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7 DCF77 AM rectifier with ATtiny25

For the DCF77 signal of 77.5 kHz from a direct receiver or for the IF of 32.768 kHz from a superhet one needs a rectifier for AM signals. Usually one uses a diode rectifier. But as diode rectifiers for AM RF/IF always have the disadvantage that their forward voltage of 0.2 to 0.3 Volt won't let them detect signal amplitudes smaller than that 0.2 to 0.3 V, I designed and built a microcontroller rectifier. This device detects amplitudes of down to 5 mVpp.

Note that this design is limited to frequencies below 100 kHz, so the device is not designed and doesn't work correct with an IF of 455 kHz or higher!

7.1 How it works

AM rectifier schematic The rectifier works with a microcontroller, here an ATtiny25, and its built-in ADC channel 3. The controller runs with its built-in RC oscillator at a clock rate of 8 MHz (CLKPR is set to 1 by software).

7.1.1 The hardware

The ADC is working in free running mode, that is: he restarts the next conversion whenever the conversion is complete. The ADC clock prescaler is at 4, so the ADC runs with 2 MHz. As each conversion in free running mode takes 13.5 cycles, the ADC works with a conversion frequency of 2 MHz / 13.5 = 148.2 kHz and one conversion lasts 6.75 µs.

The RF of 77.5 kHz or the IF of 32.768 kHz comes in as a sine wave with an amplitude between 0.0 and 5.0 Vpp. The voltage divider with the two 100kΩ resistors divides the operating voltage by two, the 1nF capacitor transfers the RF/IF to the ADC3 input of the ATtiny25, so that the sine wave produces the following 10-bit ADC conversion results from the input voltage: So all the controller has to do is to
  1. subtract 2 from the MSB of the result,
  2. if that yields the carry flag being set: to invert the result.
That rectifies the signal: negative swings will get positive, positive ones remain positive (Rectification). The result is nine bits wide (0 to 511).

This is repeated over and over again (with the ADC in free running mode) for 128 times, hence over 128 * 6.75 = 864 µs. The maximum of these 128 measurements is the highest/lowest detected amplitude of the input swing. This maximum is selected from 128 measurements of 28 (32.768 kHz, 30.5 µs per wave) or 67 (77.5 kHz, 12.9 µs per wave) sine waves, so that the maximum is very likely to be detected.

The detected maxima are added up 8 times, the result is divided by 16 to yield an 8-bit average value for the PWM's compare B value. With that the measuring time is 8 * 864 µs = 6.91 ms.


7.1.2 The Duo-LED

Duo-LED signal strength display The device can be equipped with a red/green or red/yellow duo-LED to display the results. Then display on the LED works as follows. With small amplitudes red dominates, the higher the amplitude the more green.

OCR0A and OCR0B are equal This is achieved by setting the comparer values of TC0 to the same value, the TC1’s PWM value in OCR1B. The OC0-bit-behavior is to set OC0A on the beginning of the PWM cycle and to clear the OC0A on compare match (un-inverted). The OC0B is reversed: it is set at the beginning and cleared on compare match.

This yields the following behavior: When both comparers have a compare match, the color changes from green to red. If the compare match occurs at 255, the red LED is never on.

The earlier the longer is the LED red on and the green LED off. The time over which one of the two colors are on is always 100%.

OCR0A and OCR0B are unequal If OCR0A is different from the OCR0B value, the behavior is rather different. As the OC0A output is set at PWM cycle start, while OC0B is cleared, the green LED is turned on. This stays on until OCR0A is reached: this clears OC0A and, as OC0B is also cleared, switches both LEDs off. This changes later on, when OCR0B is reached: this switches the red LED on. This remains on until the end of the PWM cycle.

This is also the case if OCR0A is larger than OCR0B: the inactive time now has both pins set. This mode reduces the brightness of both LEDs, the larger the difference between OCR0A and OCR0B the longer the pause with both LEDs off. The duration of the green on and the red on can still be altered, but only to the available rest of the time.

7.1.3 DC output

PWM RC filter response The timer/counter TC1 produces the output, a DC signal.

The averaged amplitude feeds the comparer of the 8-bit-TC1 timer that runs as PWM with the compare B in fast PWM mode. The timer is clocked by the 8 MHz controller clock and without prescaling. The PWM runs with a frequency of 31.25 kHz, one cycle lasts 32 µs. The PWM value is updated every 13.82 ms / 32 µs = 423 cycles.

On PWM cycle start the output pin OC1B is set, on reaching compare match B it is cleared (positive PWM signal). The OC1B output signal is filtered by a 3-stage RC filter with R=6k8 and C=150n. The time constant of this RC network is t = 0.69 * R * C = 0.7 ms. The diagram shows the response of the filter on startup with an 80% PWM pulse and to a level change to a 20% PWM pulse after 35 ms.

The approximately 15 to 20 ms that the RC network needs to swing to a new value is short enough to detect 100 ms long amplitude drops for a transmitted 0-bit of DCF77 and a 200 ms long voltage drop for a 1-bit.

The PWM hum of the RC network is
  1. stage 1 (VC1, red): 0.29 Vpp,
  2. stage 2 (VC2, yellow): 17 mVpp,
  3. stage 3 (VC3, green): 5 mVpp.
So the PWM noise on the third stage is roughly one digit of a 10-bit ADC result and the RC provides sufficient filtering.

Averaging over 16 measurements ensures that single failures to detect the maximum of the input signal are smoothly handled.

7.1.4 Available ressources

All drawings shown here are available as a LibreOffice Draw file here (see the last drawing for the rectifier).

The LibreOffice Calc file am-rect_tn25.ods provides all calculations that can be useful when changing the design and properties of the device (ADC sampling, clocking, RC-filter and filter response, Duo-LED configuration, etc.). Please note that if you play around with the values therein: do not increase the speed of the AD converter, the prescaler will have to 4 or higher. Otherwise the interrupt service routine is not fast enough to handle all the interrupts and blocks other program steps from being served.

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7.2 Testing

Rectifier test signal generator I've tested the rectifier by using the generator to the right. It generates a sine wave either with 77.5 kHz (no parallel C) or 32.8 kHz (1n5 parallel to the coil). The signal is not a very nice sine wave, but it fits to the rectifier.

The potentiometer in the source line of the FET allows to dim the signal strength.

Rectifier and test generator on a breadboard This is the rectifier on a test stand. Unfortunately the generator does not provide a full 5 V swing, so you do not get the Duo-LED to full green color.

7.3 Software for the rectifier

The software for the ATtiny25 is written in assembler. The source code is here in assembler source code format and here to view it in the browser. No fuses have to be changed: the increase of the clock frequency from the 1 MHz default to 8 MHz is done by software, so the fuse CKDIV8 is overwritten.

The program is interrupt-driven. No sleep mode is used because the fast ADC sampling rate eats up most of the time.

Be careful when changing "MaxCount" and/or "MaxAverage": Sampling rates might get too short (measuring might not be exact as the maximum is not found) or too long to fit to the DCF77 signal (100 ms are not very long and there should be at least seven output PWM samples available (3 for the falling edge, 3 for the rising edge, plus one extra in between).

When assembling make sure that the two settings "DuoLed" and "LedOnly" are set to your needs:

The program has been tested and works fine as designed.

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