Path: Home => AVR overview => Applications => DCF77 receivers => alarm clock m324pa   Diese Seite in Deutsch: Flag DE
DCF77 receiver logo Applications of
AVR single chip controllers AT90S, ATtiny, ATmega and ATxmega
DCF77 Alarm clock with ATmega324PA

9 DCF77 Alarm clock with ATmega324

Highly experimental! Not tested yet!

With that project I will try to integrate Connecting the alarm clock to the receiver This shows the connections of the alarm clock with the previous receiver modules. One controller here replaces three other controllers.

As this yields a full feature alarm clock, it should also include: This requires additional connections to external components, as can be see to the right of the alarm clock module.

The project is an idea and not yet finished.

9.1 Selecting the controller

In order to perform all these tasks the controller must have
  1. two PWM outputs at a high frequency for the AFC and AGC PWM,
  2. a PWM with a frequency of 100 to 200 Hz for the backlight,
  3. a 16-bit-timer in CTC mode with an OC output pin for generating the alarm tone and the music to be played,
  4. two xtal pins to clock the controller with a crystal,
  5. an 8-bit bidirectional port for the data transfer to the LCD and for reading the busy flag of the LCD as well as three single port pins for the control of the LCD,
  6. three pins for the three keys, that can interrupt whenever one of the key is pressed (either INTn or PCINTn),
  7. three analog converter inputs for RF/IF amplitude measurement (high speed ADC channel), ambient light sensor and a potentiometer to adjust date, time and alarm time digits.
As one of timers also has to provide the 5-ms pulse for DCF77 signal analysis and for the derived second pulse, I selected TC2 for that purpose. As this requires mixed CTC (to arrive at exact divider results) as well as PWM operation, OCR2B was selected for the LCD backlight PWM.

Selecting the appropriate AVR type This is avr_sim's device selection window with all necessary hardware features. Not many different devices fulfill all the required properties. All of them end with a 4. A price comparison with my preferred electronics dealer showed the ATmega324PA is my preferred selection.

9.2 The hardware

The hardware of the alarm clock This is the complete hardware schematic for the alarm clock.

The three ADC channels ADC0, ADC1 and ADC2 are connected to the following external devices: Usually the ADC measures the RF/IF amplitude in a very fast manner and is in free running mode with interrupts enabled. From time to time (the ambient light sensor every 1.28 seconds, the potentiometer every 250 ms) the free running mode and the interrupt generation is stopped and the additional ADC channel is measured in polling mode.

The device is clocked with a 4.096 MHz crystal on the XTAL1 and XTAL2 pins, so that the operation of the clock over weeks and monthes without synchronization with DCF77 is exact enough for an alarm clock and the clock does not require re-adjustment.

PWM humming on RC network The AFC- and AGC-signals are produced by OC0A and OC0B via a two-stage RC network. The PWM signal works at 16 kHz, while the RC's half frequency is by 1000-fold lower at 14.5 Hz, so that the RC networks filters the signal good enough. While the humming on the first capacitor is at 7.82 Vpp, the second capacitor is at 10 µVpp humming, as the analysis in the sheet "rc_hum" in the LibreOffice calc file here shows.

The three keys are connected to PB0, PB1 and PB2. Those have their pull-up resistors set by software and throw PCINT interrupts to be served. After a key has been pressed, further PCINT interrupts are blocked for a dead-time of 100 milli-seconds, so that no spurios signals can confuse the software.

All external components are plugged in via a 10-pin box connector, for which the pinning is given in the lower right.

To program the ATmega324PA within the system, a standard ISP6 connector has been added. This is not necessary in the final device, but eases program changes.

9.3 Mounting the alarm clock


9.4 Software for the alarm clock


9.4.1 Download of the complete software


9.4.2 Software for hardware testing

TBD Testing the crystal clock and the ISP interface

TBD Installation and testing of the LCD

TBD Testing the LEDs

TBD Testing the AFC and AGC signal generation

TBD Testing the keys

TBD Testing the speaker

TBD Testing the RF/IF rectifier

TBD Testing the ambient light sensor

TBD Testing the potentiometer


9.4.3 Software for the alarm clock Date and time

Flow chart increase seconds The time that is independent from DCF77 synchronization is derived from the system clock of 4.092 MHz by TC2. TC2 is prescaled by 256 and the CTC mode in compare A divides the clock signal by 80. That delivers a signal of f = 4.096 MHz / 256 / 80 = 200 Hz. The register rSecDiv counts from 200 down to zero. If that reaches zero, the time and date has to be advanced by one second.

Time and date is completely located at the beginning of the SRAM. Time and dates are stored in binary form, each component in one byte, in a total of seven bytes. These bytes are overwritten when DCF77 received a correct and complete time/date set.

This is the flow that increases the current time and date by one second. The algorithm to the left does the increase to the date and time components, the algorithm to the right updates all changed digits on the LCD. All software flow drawings are available in the LibreOffe draw file here.

Most of the increases are straight forward and simple. Only the calculation of the days of the current month is a little bit more complex, thanks to a pope around the year 1500.

Realization uses the pointer register pair X (R27:R26) that is increased each time the next time/date component is reached.

The display of the components on the LCD starts with setting the cursor to the line and column where the component is located. All components, excluding the day abbreviation, are displayed by calling the routine LcdDec2, that is part of the include routine for LCD operation DCF77 analysis

TBD LCD operation

TBD Adjusting date, time and alarm time with the keys


Flow weekday from date If the user adjusts the date, we can ease that by calculating the weekday from the adjusted date, so that the weekday is automatically correct. To the right you see the flow scheme of that calculation.

It is rather simple and based on the weekday on 01.01.2000, which was a Saturday. For each day and for each year since then (difference minus one) we add one to the result. The difference caused by the month are a little more complicated. It is held in a table in the flash memory. The difference to be added for each month (minus one) is read from that table. As the table is based on a non-leap-year with 365 days, we have to add one for a leap year and for the months above February. Finally we have to add the number of leap years since 2000 to the current year (minus one), which is simply the (year minus one) divided by four.

At the end we repeatedly subtract 7 until the result is smaller than 7 (Modulo calculation).

Those who want to play around with the calculation, here is the source code in asm format.

To the top of that page

©2020 by